A Low Power Four Transistor Schmitt Trigger for Asymmetric Double Gate Fully Depleted SOI Devices

IEEE International SOI Conference

Volumn , Issue , 2003, Pages 21-22

  Cakici, Tamer ^a   Bansal, Aditya ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); LEAKAGE CURRENTS; SPURIOUS SIGNAL NOISE;

POWER DISSIPATION;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0142154823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2003.1242882     Document Type: Conference Paper

References (6)

1. J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1996, pp 366-367.
2. Taurus Process & Device, V2001.4, Synopsys, Inc.
3. X. Tang et. al. "SOI MOSFET Fluctuation Limits on GSI", 1999 IEEE International SOI Conf., pp. 42-43.
4. ITRS Roadmap, http://public.itrs.net/
5. P. Ranade et. al. "Tunable Work Function Molybdenum Gate Technology for FDSOI-CMOS", 2002 IEDM, pp. 363-366.
6. Y. Omura et. al. "Quantum-Mechanical Effects on the Threshold Voltage of Ultrathin-SOI nMOSFET's", IEEE Electron Devices Letters Vol.14, pp.569-571.