Interconnect opportunities for gigascale integration

IBM Journal of Research and Development

Volumn 46, Issue 2-3, 2002, Pages 245-263

  Meindl, James D ^a   Davis, Jeffrey A ^a   Zarkesh Ha, Payman ^b   Patel, Chirag S ^c   Martin, Kevin P ^a   Kohl, Paul A ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AGERE SYSTEMS   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CHIP SCALE PACKAGES; ENERGY DISSIPATION; FABRICATION; PRODUCTIVITY; WSI CIRCUITS;

MICROPHOTONIC INTERCONNECTS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036508438     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.462.0245     Document Type: Review

References (45)

1. Low power microelectronics: Retrospect and prospect
2. A High performance 0.25 micron logic technology optimized for 1.8V operation
3. The future of interconnection technology
4. Cache-coherent distributed shared memory: Perspectives in its development and future challenges
5. On a pin versus block relationship for partition of logic paths
6. A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation
7. A stochastic wire-length distribution for gigascale integration (GSI) - Part II: Applications to clock frequency, power dissipation, and chip size estimation
8. Minimum power and area N-tier multilevel interconnect architectures using optimal repeater insertion
9. Optimal interconnect circuits for VLSI
10. Optimal interconnect circuits for VLSI
11. A compact physical via blockage model
12. Performance trends in high-end processors
13. Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
14. Compact distributed RLC interconnect models Part I: Single line transient, time delay, and overshoot expressions
15. Compact distributed RLC interconnect models Part II: Coupled line transient expressions and peak crosstalk in multilevel networks
16. Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC)
17. Closed-form expressions for interconnect delay, coupling, and crosstalk in VLSIs
18. Analytical models for coupled distributed RLC lines with ideal and non-ideal return paths
19. An integrated architecture for global interconnects in a gigascale system-on-a-chip (GsoC)
20. Wire-length distribution of three-dimensional integrated circuits
21. Interconnect performance modeling for 3D integrated circuits with multiple silicon layers
22. A three-dimensional stochastic wire length distribution for variable separation of strata
23. Three-dimensional integrated circuits for low-power, high bandwidth systems on a chip
24. Bonding wire microelectronic interconnections
25. Solid logic technology: Versatile, high-performance microelectronics
26. SLT device metallurgy and its monolithic extension
27. Performance improvements using on-board wires for on-chip interconnects
28. Low cost high density compliant wafer level package
29. Cost analysis of compliant wafer level packages
30. Compliant wafer level package (CWLP) with air-gaps for sea of leads (SoL) interconnections
31. Stochastic net length distribution for global interconnects in a heterogeneous system-on-a-chip
32. Scaling optoelectronic-VLSI circuits into the 21st century: A technology roadmap
33. Materials for monolithic silicon microphotonics
34. Silicon-based microphotonics and integrated optoelectronics
35. Silicon microphotonics
36. An efficient room-temperature silicon-based light-emitting diode
37. Optical interconnections for VLSI systems
38. Optical clock distribution in electronic systems
39. Input coupling and guided wave distribution schemes for broad-band intrachip guided wave optical clock distribution networks using volume grating coupler technology
40. Electrical measurements of individual semiconducting single-walled carbon nanotubes of various diameters
41. Special issue on distributed shared memory systems
42. Rationale and challenges for optical interconnects to electronic chips