Performance improvement using on-board wires for on-chip interconnects

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2000, Pages 325-328

  Naeemi, Azad ^a   Zarkesh Ha, Payman ^a   Patel, Chirag S ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

ON BOARD WIRES; ON CHIP INTERCONNECTS;

MICROPROCESSOR CHIPS;

EID: 0034515886     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)