Cost analysis of compliant wafer level package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2000, Pages 1634-1639

  Patel, Chirag S ^a   Realff, Matthew ^b   Merriweather, Samuel ^b   Power, Chris ^b   Martin, Kevin ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (Georgia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COSTS; SILICON WAFERS; TECHNOLOGY;

COMPLIANT WAFER LEVEL PACKAGE;

ELECTRONICS PACKAGING;

EID: 0034483098     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (0)