Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC)

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 280-281

  Naeemi, A ^a   Patel, C S ^a   Bakir, M S ^a   Zarkesh Ha, P ^a   Martin, K P ^a   Meindl, J D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; COSTS; INDUCTANCE; INTEGRATED CIRCUIT MANUFACTURE; PRINTED CIRCUIT BOARDS;

SYSTEM-ON-A-CHIPS (SOC);

MICROPROCESSOR CHIPS;

EID: 0035058589     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Low cost high density compliant wafer level package
2. Cost analysis of compliant wafer level packages
3. Stochastic net length distribution for global interconnects in a heterogeneous system-on-a-chip
4. An integrated architecture for global interconnects in a gigascale system-on-a-chip
5. Asymptotically zero power dissipation gigahertz clock distribution networks