Scanning the Issue

Proceedings of the IEEE

Volumn 87, Issue 3, 1999, Pages 399-404

[No Author Info available]

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0343653350     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/jproc.1999.747860     Document Type: Article

References (21)

1. H. Abdel-Shafi, J. Hall, S. V. Adve, V. S. Adve, "An evaluation of fine-grain producer-initiated communication in cache-coherent multiprocessors," in Proc. 3rd Int. Symp. High-Performance Computer Architecture, Feb. 1997, pp. 204-215.
2. S. Adve and K. Gharachorloo, "Shared memory consistency models: A tutorial," IEEE Comput., vol. 29, pp. 66-76, Dec. 1996.
3. G. Bell and C. van Ingren, "DSM perspective: Another point of view," this issue, pp. 412-417.
4. B. N. Bershad, M. J. Zekauskas, and W. A. Sawdon, "The midway distributed shared memory system," in COMPCON'93, Feb. 1993, pp. 528-537.
5. M. Dubois, C. Scheurich, and F. Briggs, "Memory access buffering in multiprocessors," in 16th Anmi. Int. Symp. Computer Architecture, 1986, pp. 434-442.
6. M. Dubois, J. Skeppstedt, L. Ricciulli, K. Ramamurthy, and P. Stenström, "The detection and elimination of useless misses in multiprocessors," in 20th Annu. Int. Symp. Computer Architecture, May 1993, pp. 88-97.
7. K. Gharachorloo, D. Lenoski, J. Laudon, P. Gibbons, A. Gupta, and J. Hennessy, "Memory consistency and event ordering in scalable shared-memory multiprocessors," in 17th Annu. Int. Symp. Computer Architecture, May 1990, pp. 15-26.
8. E. Hagersten, A. Landin, and S. Haridi, "DDM-A cache-only memory architecture," IEEE Compnt., vol. 25, pp. 44-54, Sept. 1992.
9. E. Hagersten and G. Papadopoulos, "Parallel computing in the commercial marketplace: Research and innovation at work," this issue, pp. 405-411.
10. L. Hammond, B. Nayfeh, and K. Olukotun, "A single-chip multiprocessor," IEEE Compnt.. vol. 30, pp. 79-85, Sept. 1997.
11. M. P. Herlihy and J. M. Wing, "Linearizability: A correctness condition for concurrent objects," ACM Trans. Programming Languages Syst., vol. 12, no. 3, pp. 463-492, 1990.
12. P. Keleher, A. L. Cox, and W. Zwaenepoel, "Lazy release consistency for software distributed shared memory," in 19th Annu. Int. Symp. Computer Architecture, May 1992, pp. 13-21.
13. L. Lamport, "How to make a multiprocessor computer that correctly executes multiprocess programs," IEEE Trans. Compnt., vol. C-28, pp. 241-248, Sept. 1979.
14. D. Lenoski, J. J. Laudon, T. Joe, D. Nakahira, L. Stevens, A. Gupta, and J. Hennessy, "The DASH prototype: Logic overhead and performance," IEEE Trans. Parallel Distrib. Syst., vol. 4, pp. 41-61, Jan. 1993.
15. T. Mowry and A. Gupta, "Tolerating latency through softwarecontrolled prefetching in shared-memory multiprocessors," J. Parallel Distrib. Compnt., vol. 12, pp. 87-106, July 1991.
16. J. Protic, M. Tomasevic, and V. Milutinovic, "Survey of distributed shared memory," IEEE Parallel Distrib. Technol., vol. 4, pp. 63-78, Summer 1996.
17. J. Protic, M. Tomasevic, and V. Milutinovic, Distributed Shared Memory: Concepts And Systems. Los Alamitos, CA: IEEE Computer Society Press, 1998.
18. S. Savic, M. Tomasevic, V. Milutinovic, A. Gupta, M. Natale, and I. Gertner, "Improved RMS for the PC environment," Microprocessor Syst., vol. 19, no. 10, pp. 609-619, Dec. 1995.
19. J. Skeppstedt and P. Stenström, "A compiler algorithm that reduces read latency in ownership-based cache coherence protocols," in Proc. Parallel Architectures and Compilation Techniques, July 1995, pp. 69-78.
20. P. Stenström, M. Brorsson, F. Dahlgren, H. Grahn, and M. Dubois, "Boosting performance of shared-memory multiprocessors," IEEE Comput., vol. 30, pp. 63-70, July 1997.
21. P. Stenström, E. Hagersten, D. Lilja, M. Martonosi, and M. Venugopal, "Trends in shared-memory multiprocessinc," IEEE Comput., vol. 30, pp. 44-50, Dec. 1997.