Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections

Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001

Volumn , Issue , 2001, Pages 151-153

  Reed, H A ^a   Bakir, M S ^b   Patel, C S ^b   Martin, K P ^b   Meindl, J D ^b   Kohl, P A ^a  

^a Georgia Institute of Technology ^*  (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85001140183     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2001.930043     Document Type: Conference Paper

References (7)

1. The International Roadmap for Semiconductors, SIA, 1999 reversion.
2. M. Bakir, C. Patel, P. Kohl, K. Martin, J. Meindl, "Ultra High I/O Density Package: Sea of Leads (SoL)." International Conference on High Density Interconnects and System Level Packaging (HDI), Apr. 2001.
3. A. Naeemi, C. Patel, M. Bakir, P. Zarkesh-Ha, K. Martin, J. Meindl, "Sea of Leads: A Disruptive Paradigm for a System-on-a-Chip", International Solid States Conference, San Francisco, CA. pp 280-281,Feb 2001.
4. C. Patel, et al.,"Low cost high density compliant wafer level package," International Conf. on High-Density Interconnect and Systems Packaging, Denver, CO, April 26-28, 2000, pp. 261-268.
5. P. Kohl et al. Electrochemical and Solid State Letters, Vol. 1, No.1, July 1998, pp. 49-51.
6. P. Zarkesh-Ha and J. Meindl, "An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)," IEEE Symposium on VLSI Technology, June 2000.
7. S. Mourad and Y. Zorian, Principles of Testing Electronic Systems, John Wiley & Sons, 2000