Cache-coherent distributed shared memory: Perspectives on its development and future challenges

Proceedings of the IEEE

Volumn 87, Issue 3, 1999, Pages 418-429

  Hennessy, John ^a   Heinrich, Mark ^b   Gupta, Anoop ^c,d  

^a STANFORD UNIVERSITY   (United States)

^b School of Operations Research and Industrial Engineering   (United States)

^c MICROSOFT RESEARCH   (United States)

^d NATIONAL ACADEMY OF ENGINEERING   (United States)

Author keywords

Cache coherence; Directory based cache coherence; Distributed shared memory; Multiprocessor architecture; Scalable multiprocessors

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; DATA RECORDING; MULTIPROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

CACHE-COHERENT DISTRIBUTED SHARED MEMORY (DSM);

BUFFER STORAGE;

EID: 0033096928     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.747863     Document Type: Article

References (27)

1. B. Ang, D. Chiou, D. Rosenband, M. Erlich, L. Rudolph, and Arvind, "StarT-Voyager: A flexible platform for exploring scalable SMP issues," in Proc. SiipcrComputinc '98, Orlando, FL.
2. A. Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, and D. Yeung, "The MIT Alewife Machine: Architecture and performance," in Proc. 22nd Int. Symp. Computer Architecture, Santa Marghcrita Liguire, Italy, June 1995, pp. 2-13.
3. T."Brewer and G. Astfalk, "The evolution of the HP/convex exemplar," in Proc. COMPCON Spring'97:42nd IEEE Computer Society Int. Conf., Feb. 1997, pp. 81-86.
4. "Butterfly parallel processor," BBN Lab., Cambridge, MA, Tech. Rep. 6148, 1986.
5. H. Burkhardt III, S. Frank, B. Knobe, and J. Rothnie, "Overview of the KSR-1 computer system," Kendall Square Research, Boston, MA, Tech. Rep. KSR-TR-9202001, Feb. 1992.
6. D. Callahan, K. Kennedy, and A. Porterfield, "Software prefetching," in Proc. 4th Int. Conf. Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, Apr. 1991, pp. 40-52.
7. L. Censier and P. Feautrier, "A new solution to coherence problems in'inulticache systems," IEEE Trans. Coinput., vol. C(27), pp :1112-1118, Dec. 1978.
8. R. Clark SCI interconnect chipset and adapter: Building large scale enterprise servers with Pentium Pro SHV nodes," Data General, Tech. Rep., 1996.
9. E. Gomish, E. Granston, and A. Veidenbaum, "Compilerdirected data prefetching in multiprocessors with memory hierarchies," in Proc. Int. Conf. Supcrcompuling, Nov. 1990, pp. 354-368.
10. E. Hagersten, A. Landin, and S. Haridi, "DDM-A cache-only memory architecture," lEEEComput., vol. 25, pp. 44-54, Sept. 1992.
11. Scalable Coherent Interface, IEEE Standard 1596-1992, Aue. 1993.
12. J. Kuskin, D. Ofelt, M. Heinrich, J. Heiniein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy, "The Stanford FLASH multiprocessor," in Proc. 21st Int. Symp. Computer Architecture, Chicago, IL, Apr. 1994, pp. 302-313.
13. L. Lamport, "How to make a multiprocessor computer that correctly executes multiprocess prosrams," IEEE Trans. Comput., vol. C-28, pp. 241-248, Sept. 1979.
14. T. Lovett and R. Clapp, "STiNG: A CC-NUMA computer system for the commercial marketplace," in Proc. 23rd Int. Symp. Computer Architecture, Philadelphia, PA, May 1996, pp. 308-317.
15. D. Lenoski, "The design and analysis of DASH: A scalable directory-based multiprocessor," Ph.D. dissertation, Stanford Univ., Sanford, CA, Tech. Rep. CSL-TR-92-507, Feb. 1992.
16. J. Laudon and D. Lenoski, "The SGI origin: A ccNUMA highly scalable server," in Proc. 24th Int. Symp. Computer Architecture, Denver, CO, June 1997, pp. 241-251.
17. D. Lenoski, J. Laudon, K. Gharachorloo, W. D. Weber, A. Gupta, and J. Hennessy, "The Stanford DASH multiprocessor," IEEE Comput., vol. 25, pp. 63-79, Mar. 1992.
18. T. C. Mowry, M. S. Lam, and A. Gupta, "Design and evaluation of a compiler algorithm for prefetching," in Proc. 5th int. Conf. Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, Oct. 1992, pp. 26-36.
19. M. Martonosi, D. Ofelt, and M. Heinrich, "Integrating performance monitoring and communication in parallel computers," in Proc. SIGMETRICS Int. Conf. Measurement and Modeling of Computer Systems, May 1996, pp. 138-147.
20. R. S. Nikhil, G. M. Papadopoulos, and Arvind, T: A multithreaded massively parallel architecture," in Proc. 19tli Annii. Symp. Computer Architecture, Gold Coast, Australia, May 1992, pp. 156-167.
21. G. F. Pfister, W. C. Brantley, D. A. George, S. L. Harvey, W. J. Kleinfelder, K. P. McAuliffe, E. A. Melton, V. A. Norton, and J. Weiss, "The IBM research parallel processor prototype (RP3): Introduction and architecture," in Proc. 1985 Conf. Parallel Processing, 1985, pp. 764-771.
22. S. Reinhardt, J. Larus, and D. Wood, "Tempest and typhoon: User-level shared memory," in Proc. 21st Int. Symp. Computer Architecture, Chicago, IL, Apr. 1994, pp. 325-336.
23. R. J. Swan, A. Bechtolsheim, K. W. Lai, and J. K. Ousterhout, "The implementation of the Cmmulti-microprocessor," in Proc. AFIPS NCC, 1977, pp. 645-654.
24. S. Scott, "Synchronization and communication in the Cray T3E multiprocessor," in Proc. 7th Int. Conf. Architectural Support for Programming Languages ami Operating Systems, Cambridge, MA, 1996, pp. 26-36.
25. J. P. Singh, W.-D. Weber, and A. Gupta, "SPLASH: Stanford parallel applications for shared-memory," Conipnt. Architecture News, vol. 20, no. 1, pp. 5-44, Mar. 1992.
26. W. D. Weber, S. Gold, P. Heiland, T. Shimizu, T. Wicki, and W. Wilke, "The Mercury interconnect architecture: A costeffective infrastructure for high-performance servers," in Proc. 24th Int. Symp. Computer Architecture, Denver, CO, June 1997, pp. 98-107.
27. S. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations," in Proc. 22nd Annu. Int. Symp. Computer Architecture, Santa Margherita Liguire, Italy, June 1995, pp. 24-36.