Analytical models for coupled distributed RLC lines with ideal and non-ideal return paths

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 689-692

  Naeemi, Azad ^a   Davis, Jeffrey A ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CROSSTALK; DELAY CIRCUITS; DIELECTRIC MATERIALS; EIGENVALUES AND EIGENFUNCTIONS; ELECTRIC CONDUCTORS; ELECTRIC NETWORK TOPOLOGY; LIGHT VELOCITY; MATRIX ALGEBRA;

CAPACITANCE MATRIX; CO-PLANAR GROUND LINES; GLOBAL INTERCONNECT STRUCTURES; RETURN PATHS;

COUPLED CIRCUITS;

EID: 0035718379     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. First-generation MAJC dual microprocessor
2. The first IA-64 Microprocessor
3. Compact distributed RLC interconnect models
4. Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis
5. Modeling and characterization of long on-chip interconnections for high-performance microprocessors
6. Interconnect Analysis Program