메뉴 건너뛰기




Volumn , Issue , 2000, Pages 126-128

A three-dimensional stochastic wire-length distribution for variable separation of strata

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; STOCHASTIC SYSTEMS;

EID: 34548043503     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2000.854301     Document Type: Conference Paper
Times cited : (44)

References (11)
  • 1
    • 0029292398 scopus 로고
    • Low Power Microelectronics: Retrospect and Prospect
    • April
    • J. D. Meindl, "Low Power Microelectronics: Retrospect and Prospect," Proc. IEEE, vol. 83, pp. 619-635, April 1995.
    • (1995) Proc. IEEE , vol.83 , pp. 619-635
    • Meindl, J.D.1
  • 4
    • 0032026510 scopus 로고    scopus 로고
    • A Stochastic Wire-length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation
    • March
    • J. A. Davis, V. K. De, J. D. Meindl, "A Stochastic Wire-length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 580-589, March 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , Issue.3 , pp. 580-589
    • Davis, J.A.1    De, V.K.2    Meindl, J.D.3
  • 5
    • 0019565820 scopus 로고
    • Wire Length Distribution for Placement of Computer Logic
    • May
    • W. E. Donath, "Wire Length Distribution for Placement of Computer Logic," IBM J. Res. Develop., vol. 2, no. 3, pp. 152-155, May 1981.
    • (1981) IBM J. Res. Develop. , vol.2 , Issue.3 , pp. 152-155
    • Donath, W.E.1
  • 7
    • 85013949634 scopus 로고    scopus 로고
    • Wire-Length Distribution of Three-Dimensional Integrated Circuits
    • A. Rahman, A. Fan, J. Chung, R. Reif, "Wire-Length Distribution of Three-Dimensional Integrated Circuits," IITC, pp.233-235, 1999.
    • (1999) IITC , pp. 233-235
    • Rahman, A.1    Fan, A.2    Chung, J.3    Reif, R.4
  • 8
    • 33646125223 scopus 로고    scopus 로고
    • Interconnect Performance Modeling for 3D Integrated Circuits with Multiple Si Layers
    • S. J. Souri, K. C. Saraswat, "Interconnect Performance Modeling for 3D Integrated Circuits with Multiple Si Layers," IITC, pp 24-26, 1999.
    • (1999) IITC , pp. 24-26
    • Souri, S.J.1    Saraswat, K.C.2
  • 9
    • 0015206785 scopus 로고
    • On a Pin Versus Block Relationship For Partitions of Logic Graphs
    • Dec.
    • B. S. Landman and R. L. Russo, "On a Pin Versus Block Relationship For Partitions of Logic Graphs," IEEE Trans. Comput., vol C-20, pp. 1469-1479, Dec. 1971.
    • (1971) IEEE Trans. Comput. , vol.C-20 , pp. 1469-1479
    • Landman, B.S.1    Russo, R.L.2
  • 10
    • 0027222295 scopus 로고
    • Closed Form Expressions for Interconnect Delay, Coupling and Crosstalk in VLSI's
    • Jan.
    • T. Sakurai, "Closed Form Expressions for Interconnect Delay, Coupling and Crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp.118-124, Jan. 1993.
    • (1993) IEEE Trans. Electron Devices , vol.40 , pp. 118-124
    • Sakurai, T.1
  • 11
    • 84962892484 scopus 로고    scopus 로고
    • Semiconductor Industry Association, "ITRS", 1999.
    • (1999) ITRS


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.