Yield prediction by sampling IC layout

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 3, 2000, Pages 359-371

  Allan, Gerard A ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC NETWORK ANALYSIS; ESTIMATION; MATHEMATICAL MODELS; POISSON DISTRIBUTION; ULSI CIRCUITS;

CRITICAL AREA EXTRACTION; EDINBURGH YIELD ESTIMATOR SAMPLING; SURVEY SAMPLING; YIELD PREDICTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034156861     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.833204     Document Type: Article

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