Integrated Circuit Yield Management and Yield Analysis: Development and Implementation

IEEE Transactions on Semiconductor Manufacturing

Volumn 8, Issue 2, 1995, Pages 95-102

  Stapper, Charles H ^a   Rosner, Raymond J ^b  

^a Industrial Consultant ^*  (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLEAN ROOMS; CMOS INTEGRATED CIRCUITS; DEFECTS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; PROBABILITY; RANDOM ACCESS STORAGE; REGRESSION ANALYSIS; RESEARCH AND DEVELOPMENT MANAGEMENT; SEMICONDUCTOR DEVICE MODELS; STATISTICAL PROCESS CONTROL;

ANALYTICAL YIELD MODELING; DEFECT DENSITY LEARNING; NEGATIVE BINOMIAL YIELD MODEL; NONLINEAR LEAST SQUARE REGRESSION ANALYSIS; YIELD ANALYSIS; YIELD MANAGEMENT;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0029304862     PISSN: 08946507     EISSN: 15582345     Source Type: Journal    
DOI: 10.1109/66.388016     Document Type: Article

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