Efficient critical area algorithms and their application to yield improvement and test strategies

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1994, Pages 88-96

  Allan, Gerard A ^a   Walton, Anthony J ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DEFECTS; ELECTRIC FAULT LOCATION; MASKS; OPTIMIZATION; PROBABILITY; REDUNDANCY; SHORT CIRCUIT CURRENTS;

FAULT CRITICAL AREA EDGES; INTEGRATED CIRCUIT MASK LAYOUT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0028747395     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)