Yield estimation model for VLSI artwork evaluation

Electronics Letters

Volumn 19, Issue 6, 1983, Pages 226-227

  Maly, W ^a   Deszczka, J ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Mask defects; Modelling; VLSI design; Yield model

Indexed keywords

INTEGRATED CIRCUITS, VLSI;

EID: 0020722214     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19830156     Document Type: Article

References (6)

1. MEAD, C., and CONWAY, L.: ‘Introduction to VLSI systems’ (Addison-Wesley, 1980), Chap. 2, pp. 47-51
2. MURPHY, B. T.: ‘Cost-size optima of monolithic integrated circuits’, IEEE Proc., 1964, 52, pp. 1537-1545
3. SCHNITZER, A. P.: ‘Automatic yield prediction from photomask inspection data’, SPIE, 1980, 221, pp. 132-139
4. RUNG, R. D.: ‘Determining IC layout rules for cost minimization’, IEEE J. Solid-State Circuits, 1981, SC-16, pp. 35-43
5. PAPOLIS, A.: ‘Probability, random variables and stochastic processes’ (McGraw-Hill, 1965), Chap. 3, pp. 71-72
6. UNSAY, B. W., and PREAS: ‘Design rule checking and analysis of IC masks design’. Proceedings Design Automation Conference, June 1975, pp. 389-393