메뉴 건너뛰기




Volumn 8, Issue 2, 1995, Pages 121-129

Quality and Reliability Impact of Defect Data Analysis

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; DEFECTS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MOS DEVICES; QUALITY ASSURANCE; RELIABILITY; SEMICONDUCTOR DEVICE MODELS;

EID: 0029308749     PISSN: 08946507     EISSN: 15582345     Source Type: Journal    
DOI: 10.1109/66.382275     Document Type: Article
Times cited : (17)

References (34)
  • 1
    • 0021444258 scopus 로고
    • Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI
    • T. E. Mangir, “Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI,” Proc. IEEE, vol. 72, no. 6, pp. 690-708, 1984.
    • (1984) Proc. IEEE , vol.72 , Issue.6 , pp. 690-708
    • Mangir, T.E.1
  • 2
    • 0022583080 scopus 로고
    • VLSI yield prediction and estimation: A unified framework
    • Jan.
    • W. Maly, A. J. Strojwas, and S. W. Director, “VLSI yield prediction and estimation: A unified framework,” IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, pp. 114-130, Jan. 1986.
    • (1986) IEEE Trans. Computer-Aided Design , vol.CAD-5 , Issue.1 , pp. 114-130
    • Maly, W.1    Strojwas, A.J.2    Director, S.W.3
  • 3
    • 84942007734 scopus 로고
    • MOS-IC process and device characterization within Philips
    • Feb.
    • S. Swaving, A. Ketting, and A. Trip, “MOS-IC process and device characterization within Philips,” IEEE Proc. Microelectronic Test Structures, vol. 1, no. 1, pp. 180-184, Feb. 1988.
    • (1988) IEEE Proc. Microelectronic Test Structures , vol.1 , Issue.1 , pp. 180-184
    • Swaving, S.1    Ketting, A.2    Trip, A.3
  • 6
    • 0023331204 scopus 로고
    • Practical defect reduction in an MOS IC line
    • Apr.
    • H. G. Claudius, “Practical defect reduction in an MOS IC line,” Microcontamination, vol. 5, no. 4, pp. 47-52, Apr. 1987.
    • (1987) Microcontamination , vol.5 , Issue.4 , pp. 47-52
    • Claudius, H.G.1
  • 7
    • 0026254278 scopus 로고
    • Defect size distribution in VLSI chips
    • Nov.
    • R. Glang, “Defect size distribution in VLSI chips,” IEEE Trans. Semicond. Manufact., vol. 4, no. 4, pp. 265-269, Nov. 1991.
    • (1991) IEEE Trans. Semicond. Manufact , vol.4 , Issue.4 , pp. 265-269
    • Glang, R.1
  • 8
    • 84942007997 scopus 로고
    • Electrical defect monitoring for process control
    • Inspection, and Process Control
    • C. F. King, G. P. Gill, and M. J. Satterfield, “Electrical defect monitoring for process control,” Integrated Circuit Metrology, Inspection, and Process Control, vol. 1087, pp. 76-82, 1989.
    • (1989) Integrated Circuit Metrology , vol.1087 , pp. 76-82
    • King, C.F.1    Gill, G.P.2    Satterfield, M.J.3
  • 9
    • 0024056631 scopus 로고
    • Circuit layout and yield
    • Aug.
    • C. Kooperberg, “Circuit layout and yield,” IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 887-892, Aug. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.23 , Issue.4 , pp. 887-892
    • Kooperberg, C.1
  • 10
    • 0348022711 scopus 로고
    • Characterization of type, size and density of spot defects in the metalization layer
    • W. Moore, W. Maly, and A. Strojwas, Eds., Philadelphia, PA: Adam Hilger
    • W. Maly, M. Thomas, J. Chinn, and D. Campbell, “Characterization of type, size and density of spot defects in the metalization layer,” in Yield Modelling and Defect Tolerance in VLSI, W. Moore, W. Maly, and A. Strojwas, Eds., Philadelphia, PA: Adam Hilger, 1988, pp. 71-90.
    • (1988) Yield Modelling and Defect Tolerance in VLSI , pp. 71-90
    • Maly, W.1    Thomas, M.2    Chinn, J.3    Campbell, D.4
  • 11
    • 84942009192 scopus 로고
    • Combining electrical defect monitors with automatic visual inspection systems
    • Inspection, and Process Control
    • C. W. Teutsch and D. C. Drain, “Combining electrical defect monitors with automatic visual inspection systems,” Integrated Circuit Metrology, Inspection, and Process Control, vol. 1087, pp. 189-199, 1989.
    • (1989) Integrated Circuit Metrology , vol.1087 , pp. 189-199
    • Teutsch, C.W.1    Drain, D.C.2
  • 13
    • 0020735104 scopus 로고
    • Integrated circuit yield statistics
    • Apr.
    • C. H. Stapper, F. M. Armstrong, and K. Saji, “Integrated circuit yield statistics,” Proc. IEEE, vol. 71, no. 4, pp. 453-470, Apr. 1983.
    • (1983) Proc. IEEE , vol.71 , Issue.4 , pp. 453-470
    • Stapper, C.H.1    Armstrong, F.M.2    Saji, K.3
  • 14
    • 0022117706 scopus 로고
    • Role of defect size distribution in yield modeling
    • Sept.
    • A. V. Ferris-Prabhu, “Role of defect size distribution in yield modeling,” IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1727-1736, Sept. 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.9 , pp. 1727-1736
    • Ferris-Prabhu, A.V.1
  • 15
    • 0022102574 scopus 로고
    • Modeling the critical area in yield forecasts
    • Aug.
    • “Modeling the critical area in yield forecasts,” IEEE J. Solid-State Circuits, vol. SC-20, no. 4, pp. 874-878, Aug. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , Issue.4 , pp. 874-878
  • 16
    • 0021466353 scopus 로고
    • Modeling of defects in integrated circuit photolithographic patterns
    • July
    • C. H. Stapper, “Modeling of defects in integrated circuit photolithographic patterns,” IBM J. Res. Develop., vol. 28, no. 4, pp. 461-475, July 1984.
    • (1984) IBM J. Res. Develop , vol.28 , Issue.4 , pp. 461-475
    • Stapper, C.H.1
  • 17
    • 0024714926 scopus 로고
    • On the design and implementation of a wafer yield editor
    • J. Pineda de Gyvez and J. A. G. Jess, “On the design and implementation of a wafer yield editor,” IEEE Trans. Computer-Aided Design, vol. 8, no. 8, pp. 920-925, 1989.
    • (1989) IEEE Trans. Computer-Aided Design , vol.8 , Issue.8 , pp. 920-925
    • Pineda de Gyvez, J.1    Jess, J.A.G.2
  • 18
    • 0024628599 scopus 로고
    • Report and User's Manual, EUT Report 89-E-216, Eindhoven University of Technology, The Netherlands, Mar.
    • J. Pineda de Gyvez, LASER: A Layout Sensitivity Explorer; Report and User's Manual, EUT Report 89-E-216, Eindhoven University of Technology, The Netherlands, Mar. 1989.
    • (1989) LASER: A Layout Sensitivity Explorer
    • Pineda de Gyvez, J.1
  • 19
    • 0025433611 scopus 로고
    • The use and evaluation of yield models in integrated circuit manufacturing
    • May
    • J. A. Cunningham, “The use and evaluation of yield models in integrated circuit manufacturing,” IEEE Trans. Semicond. Manufact., vol. 3, no. 2, pp. 60-71, May 1990.
    • (1990) IEEE Trans. Semicond. Manufact , vol.3 , Issue.2 , pp. 60-71
    • Cunningham, J.A.1
  • 20
    • 0024629198 scopus 로고
    • Large-area fault clusters and fault tolerance in VLSI circuits: A review
    • Mar.
    • C. H. Stapper, “Large-area fault clusters and fault tolerance in VLSI circuits: A review,” IBM J. Res. Develop., vol. 33, no. 2, pp. 162-173, Mar. 1989.
    • (1989) IBM J. Res. Develop , vol.33 , Issue.2 , pp. 162-173
    • Stapper, C.H.1
  • 21
    • 0022201294 scopus 로고
    • Inductive fault analysis of MOS integrated circuits
    • Dec.
    • J. P. Shen, W. Maly, and F. J. Ferguson, “Inductive fault analysis of MOS integrated circuits,” IEEE Design Test, vol. 2, no. 6, pp. 13-26, Dec. 1985.
    • (1985) IEEE Design Test , vol.2 , Issue.6 , pp. 13-26
    • Shen, J.P.1    Maly, W.2    Ferguson, F.J.3
  • 22
    • 0024108354 scopus 로고
    • A CMOS fault extractor for inductive fault analysis
    • Nov.
    • F. J. Ferguson and J. P. Shen, “A CMOS fault extractor for inductive fault analysis,” IEEE Trans. Computer-Aided Design, vol. 7, no. 11, pp. 1181-1194, Nov. 1988.
    • (1988) IEEE Trans. Computer-Aided Design , vol.7 , Issue.11 , pp. 1181-1194
    • Ferguson, F.J.1    Shen, J.P.2
  • 23
    • 0024942221 scopus 로고
    • Process monitoring oriented IC testing
    • W. Maly and S. B. Naik, “Process monitoring oriented IC testing,” in IEEE Proc. Int. Test Conf, 1989, pp. 527-532.
    • (1989) IEEE Proc. Int. Test Conf , pp. 527-532
    • Maly, W.1    Naik, S.B.2
  • 25
    • 0027609172 scopus 로고
    • Failure analysis of high density CMOS SRAMs using realistic defect modeling and iddq testing
    • June
    • S. Naik, F. Agricola, and W. Maly, “Failure analysis of high density CMOS SRAMs using realistic defect modeling and iddq testing,” IEEE Design Test, pp. 13-23, June 1993.
    • (1993) IEEE Design Test , pp. 13-23
    • Naik, S.1    Agricola, F.2    Maly, W.3
  • 26
    • 0024124138 scopus 로고
    • Fault modeling and test algorithm development for static random access memories
    • R. Dekker, F. Beenker, and L. Thijssen, “Fault modeling and test algorithm development for static random access memories,” in IEEE Proc. Int. Test Conf, 1988, pp. 343-352.
    • (1988) IEEE Proc. Int. Test Conf , pp. 343-352
    • Dekker, R.1    Beenker, F.2    Thijssen, L.3
  • 27
    • 0026676973 scopus 로고
    • Fault modeling for the testing of mixed integrated circuits
    • A. Meixner and W. Maly, “Fault modeling for the testing of mixed integrated circuits,” in IEEE Proc. Int. Test Conf, 1991, pp. 564-572.
    • (1991) IEEE Proc. Int. Test Conf , pp. 564-572
    • Meixner, A.1    Maly, W.2
  • 29
    • 33749928497 scopus 로고
    • Reliability aspects of defect analysis
    • E. M. J. G. Bruls, “Reliability aspects of defect analysis,” in IEEE Proc. Eur. Test Conf, 1993, pp. 17-26.
    • (1993) IEEE Proc. Eur. Test Conf , pp. 17-26
    • Bruls, E.M.J.G.1
  • 31
    • 0026618712 scopus 로고
    • The behavior and testing implications of CMOS IC logic gate open circuits
    • C. L. Henderson, J. M. Soden, and C. F. Hawkins, “The behavior and testing implications of CMOS IC logic gate open circuits,” in IEEE Proc. Int. Test Conf, 1991, pp. 302-310.
    • (1991) IEEE Proc. Int. Test Conf , pp. 302-310
    • Henderson, C.L.1    Soden, J.M.2    Hawkins, C.F.3
  • 32
    • 0026677929 scopus 로고
    • ‘Resistive shorts’ within CMOS gates
    • H. Hao and E. J. McCluskey, “‘Resistive shorts’ within CMOS gates,” in IEEE Proc. Int. Test Conf, 1991, pp. 292-301.
    • (1991) IEEE Proc. Int. Test Conf , pp. 292-301
    • Hao, H.1    McCluskey, E.J.2
  • 33
    • 10444284143 scopus 로고
    • Locating high resistive shorts in CMOS circuits by analyzing supply current measurement vectors
    • D. J. Burns, “Locating high resistive shorts in CMOS circuits by analyzing supply current measurement vectors,” in Proc. 1989 Int. Symp. Test Failure Anal., 1989, pp. 231-237.
    • (1989) Proc. 1989 Int. Symp. Test Failure Anal , pp. 231-237
    • Burns, D.J.1
  • 34
    • 84902479700 scopus 로고
    • A multivalued algebra for modeling physical failures in MOS VLSI circuits
    • July
    • P. Banerjee and J. Abraham, “A multivalued algebra for modeling physical failures in MOS VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-4, no. 3, pp. 312-321, July 1985.
    • (1985) IEEE Trans. Computer-Aided Design , vol.CAD-4 , Issue.3 , pp. 312-321
    • Banerjee, P.1    Abraham, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.