Component level yield / cost model for predicting VLSI manufacturability on designs using mixed technologies, circuitry, and redundancy

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1994, Pages 313-316

  Domer, Steven M ^a   Foertsch, Samuel A ^a   Raskin, Glenn D ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COSTS; DEFECTS; ELECTRIC NETWORK PARAMETERS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; REDUNDANCY; SEMICONDUCTOR DEVICE MODELS;

BACKEND COST; BACKEND YIELD; CRITICAL FACTORS; FLOORPLANNING; MANUFACTURABILITY;

VLSI CIRCUITS;

EID: 0028115165     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)