An Yield Improvement Technique for IC Layout Using Local Design Rules

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 11, 1992, Pages 1355-1362

  Allan, Gerard A ^a   Walton, Anthony J ^a   Holwill, Robert J ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; PERFORMANCE; RELIABILITY;

INTEGRATED CIRCUIT YIELD; LAYOUT DATA STRUCTURE; LOCAL DESIGN RULES; OPTIMUM FEATURE SIZE/SPACING; YIELD IMPROVEMENT TECHNIQUE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0026943255     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.177399     Document Type: Article

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