Yield prediction using calibrated critical area modelling

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1997, Pages 7-10

  Gaston, G J ^a   Allan, G A ^a  

^a Plessey Semiconductors   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; COMPUTER SOFTWARE; DEFECTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN;

CRITICAL AREA MODELLING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030679246     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)