Design of efficient BIST test pattern generators for delay testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1568-1575

  Chen, Chih Ang ^a   Gupta, Sandeep K ^b  

^a SUN MICROSYSTEMS   (United States)

^b University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; FAILURE ANALYSIS; FUNCTIONS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; NUMBER THEORY; POLYNOMIALS; SHIFT REGISTERS;

BENCHMARK CIRCUITS; BUILT IN SELF TEST PATTERN GENERATORS;

COMBINATORIAL CIRCUITS;

EID: 0030406729     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552090     Document Type: Article

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