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Volumn C-32, Issue 12, 1983, Pages 1145-1150

Exhaustive Test Pattern Generation with Constant Weight Vectors

Author keywords

Constant weight codes; exhaustive testing; fault testing; logic testing; multilevel logic; scan path; self testing; test pattern generation; VLSI testing

Indexed keywords

LOGIC CIRCUITS;

EID: 0020929233     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1983.1676175     Document Type: Article
Times cited : (65)

References (9)
  • 1
    • 0019397717 scopus 로고
    • LSI logic testing–An overview
    • Jan.
    • E. I. Muehldorf and A. D. Savkar, “LSI logic testing–An overview,” IEEE Trans. Comput., vol. C-30, pp. 1-17, Jan. 1981.
    • (1981) IEEE Trans. Comput. , vol.C-30 , pp. 1-17
    • Muehldorf, E.I.1    Savkar, A.D.2
  • 2
    • 0019634515 scopus 로고
    • Multiple fault testing of large circuits by single fault test sets
    • Nov.
    • V. K. Agarwal and A. S. F. Fung, “Multiple fault testing of large circuits by single fault test sets,” IEEE Trans. Comput., vol. C-30, pp. 855-865, Nov. 1981.
    • (1981) IEEE Trans. Comput. , vol.C-30 , pp. 855-865
    • Agarwal, V.K.1    Fung, A.S.F.2
  • 7
    • 0019899097 scopus 로고
    • Design for testability–A survey
    • Jan.
    • T. W. William and K. P. Parker, “Design for testability–A survey,” IEEE Trans. Comput., vol. C-31, pp. 2-15, Jan. 1982.
    • (1982) IEEE Trans. Comput. , vol.C-31 , pp. 2-15
    • William, T.W.1    Parker, K.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.