Methodology to design efficient BIST test pattern generators

IEEE International Test Conference (TC)

Volumn , Issue , 1995, Pages 814-823

  Chen, Chih Ang ^a   Gupta, Sandeep K ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; ELECTRIC NETWORK ANALYSIS; FEEDBACK; MICROPROCESSOR CHIPS; POLYNOMIALS; SHIFT REGISTERS; VLSI CIRCUITS;

BUILT IN SELF TEST; DETERMINISTIC TEST SET EMBEDDING; EXHAUSTIVE TESTING; OUTPUT RESPONSE ANALYZER; PSEUDO EXHAUSTIVE TESTING; PSEUDORANDOM TESTING; TEST PATTERN GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 0029521597     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (28)