Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2016-December, Issue , 2016, Pages

  Asghari Moghaddam, Hadi ^a   Son, Young Hoon ^b   Ahn, Jung Ho ^b   Kim, Nam Sung ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATION; BANDWIDTH; COMPUTATION THEORY; COMPUTER ARCHITECTURE; DATA TRANSFER; MEMORY ARCHITECTURE;

LIMITED CAPACITY; MEMORY CAPACITY; MEMORY CHANNELS; MEMORY SYSTEMS; MICRO ARCHITECTURES; PERFORMANCE OF COMPUTER SYSTEM; POWER CONSTRAINTS; TRANSFER ENERGY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 85006762808     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2016.7783753     Document Type: Conference Paper

References (65)

1. "CORAL Benchmark Codes." [Online]. Available: https://asc.llnl.gov/CORAL-benchmarks/
2. "Samsung DDR4 SDRAM." [Online]. Available: http://www.samsung.com/global/business/semiconductor/product/dram
3. "JEDEC Standard: DDR2 SDRAM Fully Buffered DIMM (FBDIMM) Design Specification, " 2007.
4. "JEDEC Standard: DDR4 SDRAM, " 2012.
5. "JEDEC Standard: DDR4 SDRAM Load Reduced DIMM (LRDIMM) Design Specification, " 2014.
6. "JEDEC Standard: Low Power Double Data Rate 4 (LPDDR4), " 2014.
7. E. Azarkhish, D. Rossi, I. Loi, and L. Benini, "A Logic-base Interconnect for Supporting Near Memory Computation in the Hybrid Memory Cube, " in Workshop on Near-Data Processing, Dec 2014.
8. S.-J. Bae, Y.-S. Sohn, K. ll Park, K.-H. Kim, D.-H. Chung, J.-G. Kim, S.-H. Kim, M.-S. Park, J.-H. Lee, S.-Y. Bang, H.-K. Lee, I.-S. Park, J.-S. Kim, D.-H. Kim, H.-R. Kim, Y.-J. Shin, C.-G. Park, G.-S. Moon, K.-W. Yeom, K.-Y. Kim, J.-Y. Lee, H.-J. Yang, S.-J. Jang, J. S. Choi, Y.-H. Jun, and K. Kim, "A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques, " in IEEE International Solid-State Circuits Conference (ISSCC), Feb 2008.
9. A. Basu, J. Gandhi, J. Chang, M. D. Hill, and M. M. Swift, "Efficient Virtual Memory for Big Memory Servers, " in ISCA, June 2013.
10. S. Borkar, "Role of Interconnects in the Future of Computing, " IEEE Journal of Lightwave Technology, vol. 31, no. 24, Dec 2013.
11. D. W. Chang, G.-s. Byun, H. Kim, M. Ahn, S. Ryu, N. Kim, and M. Schulte, "Reevaluating the Latency Claims of 3D Stacked Memories, " in IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2013.
12. D. W. Chang, Y. H. Son, J. Ahn, H. Kim, M. Ahn, M. J. Schulte, and N. S. Kim, "Dynamic bandwidth scaling for embedded DSPs with 3Dstacked DRAM and wide I/Os, " in ICCAD, 2013.
13. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron, "Rodinia: A Benchmark Suite for Heterogeneous Computing, " in IISWC, Oct 2009.
14. M. L. Chu, N. Jayasena, D. P. Jang, and M. Ignatowski, "Highlevel Programming Model Abstractions for Processing in Memory, " in Workshop on Near-Data Processing, Dec 2013.
15. M. F. Deering, S. A. Schlapp, and M. G. Lavelle, "FBRAM: A New Form of Memory Optimized for 3D Graphics, " in ACM Conference on Computer Graphics and Interactive Techniques (SIGGRAPH), Jul 1994.
16. P. Dlugosch, D. Brown, P. Glendenning, M. Leventhal, and H. Noyes, "An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing, " IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 25, no. 12, Dec 2014.
17. J. Draper, J. Chame, M. Hall, C. Steele, T. Barrett, J. LaCoss, J. Granacki, J. Shin, C. Chen, C. W. Kang, I. Kim, and G. Daglikoca, "The Architecture of the DIVA Processing-in-memory Chip, " in ICS, Jun 2002.
18. J. Ekanayake, S. Pallickara, and G. Fox, "Mapreduce for Data Intensive Scientific Analyses, " in IEEE International Conference on eScience, Dec 2008.
19. D. G. Elliott, W. M. Snelgrove, and M. Stumm, "Computational RAM: A Memory-SIMD Hybrid and its Application to DSP, " in IEEE Custom Integrated Circuits Conference (CICC), May 1992.
20. A. Farmahini-Farahani, J. Ahn, K. Morrow, and N. S. Kim, "NDA: Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules, " in HPCA, Feb 2015.
21. B. Ganesh, A. Jaleel, D. Wang, and B. Jacob, "Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling, " in HPCA, Feb 2007.
22. Q. Guo, X. Guo, R. Patel, E. Ipek, and E. Friedman, "AC-DIMM: Associative Computing with STT-MRAM, " in ISCA, Jun 2013.
23. Q. Guo, X. Guo, Y. Bai, and E. Ipek, "A Resistive TCAM Accelerator for Data-intensive Computing, " in MICRO, Dec 2011.
24. P. Hammarlund, A. Martinez, A. Bajwa, D. Hill, E. Hallnor, H. Jiang, M. Dixon, M. Derr, M. Hunsaker, R. Kumar, R. Osborne, R. Rajwar, R. Singhal, R. DSa, R. Chappell, S. Kaushik, S. Chennupaty, S. Jourdan, S. Gunther, T. Piazza, and T. Burton, "Haswell: The Fourth-Generation Intel Core Processor, " IEEE Micro, vol. 34, no. 2, Mar 2014.
25. R. Ho, K. Mai, and M. Horowitz, "The Future of Wires, " Proceedings of the IEEE, vol. 89, no. 4, Apr 2001.
26. Inphi, "Introducing LRDIMM-A New Class of Memory Modules." [Online]. Available: https://www.inphi.com/products/whitepapers/InphiLRDIMMwhitepaperFinal.pdf
27. Y.-C. Jang, H. Chung, Y. Choi, H. Park, J. Kim, S. Lim, J. Sunwoo, M.-S. Park, H.-S. Kim, S.-Y. Kim, Y.-S. Lee, W.-S. Kim, J.-B. Lee, J. Yoo, and C. Kim, "BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application with DIMM Channel, " IEEE Journal of Solid-State Circuits, vol. 44, no. 11, Nov 2009.
28. Y. Kang, W. Huang, S.-M. Yoo, D. Keen, Z. Ge, V. Lam, P. Pattnaik, and J. Torrellas, "FlexRAM: Toward an Advanced Intelligent Memory System, " in IEEE International Conference on Computer Design (ICCD), Oct 1999.
29. S. W. Keckler, W. J. Dally, B. Khailany, M. Garland, and D. Glasco, "GPUs and the Future of Parallel Computing, " IEEE Micro, vol. 31, no. 5, Sep 2011.
30. G. Kim, J. Kim, J. H. Ahn, and J. Kim, "Memory-centric System Interconnect Design with Hybrid Memory Cubes, " in International Conference on Parallel Architectures and Compilation Techniques(PACT), 2013.
31. Y. Kim, M. Papamichael, O. Mutulu, and M. Harchol-Balter, "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior, " in MICRO, Dec 2010.
32. R. Landaverde, T. Zhang, A. Coskun, and M. Herbordt, "An Investigation of Unified Memory Access Performance in CUDA, " in IEEE High Performance Extreme Computing Conference (HPEC), Sep 2014.
33. D. U. Lee, K. W. Kim, K. W. Kim, H. Kim, J. Y. Kim, Y. J. Park, J. H. Kim, D. S. Kim, H. B. Park, J. W. Shin, J. H. Cho, K. H. Kwon, M. J. Kim, J. Lee, K. W. Park, B. Chung, and S. Hong, "25.2 A 1.2V 8Gb 8-channel 128GB/s High-bandwidth Memory (HBM) Stacked DRAM with Effective Microbump I/O Test Methods Using 29nm Process and TSV, " in IEEE International Solid-State Circuits Conference (ISSCC), Feb 2014.
34. D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu, "Adaptive-latency DRAM: Optimizing DRAM Timing for the Common-case, " in HPCA, 2015.
35. S. Li, J. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, "The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing, " ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 1, Apr 2013.
36. G. Loh, N. Jayasena, M. Oskin, M. Nutter, D. Roberts, M. Meswani, D. Zhang, and M. Ignatowski, "A Processing in Memory Taxonomy and a Case for Studying Fixed-function PIM, " in Workshop on Near-Data Processing, Dec 2013.
37. G. H. Loh, "3D-Stacked Memory Architectures for Multi-core Processors, " in ISCA, Jun 2008.
38. D. Luebke, "CUDA: Scalable Parallel Programming for Highperformance Scientific Computing, " in IEEE International Symposium on Biomedical Imaging: From Nano to Macro (ISBI), May 2008.
39. K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally, and M. Horowitz, "Smart Memories: A Modular Reconfigurable Architecture, " in ISCA, Jun 2000.
40. K. T. Malladi, B. C. Lee, F. A. Nothaft, C. Kozyrakis, K. Periyathambi, and M. Horowitz, "Towards Energy-proportional Datacenter Memory with Mobile DRAM, " in ISCA, 2012.
41. B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, "ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix, " in Field Programmable Logic and Application, 13th International Conference, 2003.
42. Micron, "Micron Z80A 4Gb DDR4 x8 Package DQ S-parameters, " 2015. [Online]. Available: http://www.micron.com/media/documents/products/sim-model/dram/z80ax8dqsparam.zip
43. R. Oh, B. Lee, S.-W. Shin, W. Bae, H. Choi, I. Song, Y.-S. Lee, J.-H. Choi, C.-W. Kim, S.-J. Jang, and J. S. Choi, "Design Technologies for a 1.2V 2.4Gb/s/pin High Capacity DDR4 SDRAM with TSVs, " in IEEE Symposium on VLSI Circuits, Jun 2014.
44. M. Oskin, F. Chong, and T. Sherwood, "Active Pages: A Computation Model for Intelligent Memory, " in ISCA, Jun 1998.
45. A. Parashar, M. Pellauer, M. Adler, B. Ahsan, N. Crago, D. Lustig, V. Pavlov, A. Zhai, M. Gambhir, A. Jaleel, R. Allmon, R. Rayess, S. Maresh, and J. Emer, "Triggered Instructions: A Control Paradigm for Spatially-programmed Architectures, " in ISCA, Jun 2013.
46. D. Patterson, K. Asanovic, A. Brown, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, C. Kozyrakis, D. Martin, S. Perissakis, R. Thomas, N. Treuhaft, and K. Yelick, "Intelligent RAM (IRAM): The Industrial Setting, Applications, and Architectures, " in IEEE International Conference on Computer Design (ICCD), Oct 1997.
47. D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick, "A Case for Intelligent RAM, " IEEE Micro, vol. 17, no. 2, Mar 1997.
48. J. T. Pawlowski, "Hybrid Memory Cube, " in Hot Chips, Aug 2011.
49. S. H. Pugsley, J. Jestes, R. Balasubramonian, V. Srinivasan, A. Buyuktosunoglu, A. Davis, and F. Li, "Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads, " IEEE Micro, vol. 34, no. 4, Jul 2014.
50. S. H. Pugsley, J. Jestes, H. Zhang, R. Balasubramonian, V. Srinivasan, A. Buyuktosunoglu, A. Davis, and F. Li, "Ndc: Analyzing the impact of 3d-stacked memory+ logic devices on mapreduce workloads, " in ISPASS, 2014.
51. R. Sampson, M. Yang, S. Wei, C. Chakrabarti, and T. F. Wenisch, "Sonic Millip3De: A Massively Parallel 3D-stacked Accelerator for 3D Ultrasound, " in HPCA, Feb 2013.
52. A. Sodani, "Rethinking Design Metrics for Datacenter DRAM, " in ACM International Symposium on Memory Systems (MEMSYS), 2015, pp. 162-163.
53. J. E. Stone, D. Gohara, and G. Shi, "OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems, " IEEE Computing in Science & Engineering, vol. 12, no. 3, May 2010.
54. J. A. Stratton, C. Rodrigues, I.-J. Sung, N. Obeid, L.-W. Chang, N. Anssari, G. D. Liu, and W.-M. Hwu, "Parboil: A Revised Benchmark Suite for Scientific and Commercial Throughput Computing, " Center for Reliable and High-Performance Computing, Mar 2012.
55. S. K. Venkata, I. Ahn, D. Jeon, A. Gupta, C. Louie, S. Garcia, S. Belongie, and M. B. Taylor, "SD-VBS: The San Diego Vision Benchmark Suite, " in IISWC, Oct 2009.
56. F. A. Ware and C. Hampel, "Improving Power and Data Efficiency with Threaded Memory Modules, " in IEEE International Conference on Computer Design (ICCD), Oct 2006.
57. M. Watkins and D. Albonesi, "ReMAP: A Reconfigurable Heterogeneous Multicore Architecture, " in MICRO, Dec 2010.
58. K. Wilcox, D. Akeson, H. Fair, J. Farrell, D. Johnson, G. Krishnan, H. Mclntyre, E. McLellan, S. Naffziger, R. Schreiber, S. Sundaram, and J. White, "A 28nm x86 APU Optimized for Power and Area Efficiency, " in IEEE International Solid-State Circuits Conference (ISSCC), Feb 2015.
59. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations, " in ISCA, Jun 1995.
60. D. H. Yoon, J. Chang, N. Muralimanohar, and P. Ranganathan, "BOOM: Enabling Mobile Memory Based Low-Power Server DIMMs, " in ISCA, Jun 2012.
61. D. H. Yoon and M. Erez, "Virtualized and Flexible ECC for Main Memory, " in ASPLOS, Mar 2010.
62. D. H. Yoon, M. K. Jeong, and M. Erez, "Adaptive Granularity Memory Systems: A Tradeoff between Storage Efficiency and Throughput, " in ISCA, Jun 2011.
63. D. Zhang, N. Jayasena, A. Lyashevsky, J. L. Greathouse, L. Xu, and M. Ignatowski, "TOP-PIM: Throughput-oriented Programmable Processing in Memory, " in ACM International Symposium on Highperformance Parallel and Distributed Computing (HPDC), Jun 2014.
64. H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu, "Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency, " in MICRO, Nov 2008.
65. Q. Zhu, B. Akin, H. E. Sumbul, F. Sadi, J. C. Hoe, L. Pileggi, and F. Franchetti, "A 3D-stacked Logic-in-memory Accelerator for Application-Specific Data Intensive Computing, " in IEEE International 3D Systems Integration Conference (3DIC), Oct 2013.