Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015

Volumn , Issue , 2015, Pages 489-501

  Lee, Donghyuk ^a   Kim, Yoongu ^a   Pekhimenko, Gennady ^a   Khan, Samira ^a   Seshadri, Vivek ^a   Chang, Kevin ^a   Mutlu, Onur ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MANUFACTURE; TIMING CIRCUITS;

IMPROVE PERFORMANCE; MINIMUM LATENCIES; OPERATING CONDITION; PROCESS VARIATION; RELIABLE OPERATION; TESTING PLATFORMS; TIMING PARAMETERS; WORST CASE SCENARIO;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84934293438     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2015.7056057     Document Type: Conference Paper

References (76)

1. Memcached. http://memcached. org/.
2. PARSEC Benchmarks. http://parsec. cs. princeton. edu/.
3. The Apache HTTP Server Project. http://httpd. apache. org/.
4. J.-H. Ahn et al. Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications. In ASSCC, 2006.
5. AMD. AMD Opteron 4300 Series processors. http://www. amd. com/en-us/products/server/4000/4300.
6. AMD. BKDG for AMD Family 16h Models 00h-0Fh Processors, 2013.
7. K. Chandrasekar et al. Exploiting Expendable Process-margins in DRAMs for Run-time Performance Optimization. In DATE, 2014.
8. K.-W. Chang et al. Improving DRAM performance by parallelizing refreshes with accesses. In HPCA, 2014.
9. H. David et al. Memory power management via dynamic voltage/ frequency scaling. In ICAC, 2011.
10. Dell. Dell PowerEdge R415 Spec Sheet. http://www. dell. com/ learn/us/en/04/shared-contentdata-sheetsen/ documentsr415-specsheet. pdf, 2009.
11. N. El-Sayed et al. Temperature Management in Data Centers: Why Some (Might) Like It Hot. In SIGMETRICS, 2012.
12. N. El-Sayed et al. Temperature Management in Data Centers: Why Some (Might) Like It Hot. In Technical Report, CSRG-615, University of Toronto, 2012.
13. P. Friedberg et al. Modeling within-die spatial correlation effects for process-design co-optimization. In ISQED, 2005.
14. P. Gillingham et al. High-speed, high-reliability circuit design for megabit DRAM. In JSSC, 1991.
15. T. Hamamoto et al. On the Retention Time Distribution of Dynamic Random Access Memory (DRAM). In IEEE TED, 1998.
16. H. Hidaka et al. The cache DRAM architecture: A DRAM with an onchip cache memory. IEEE Micro, March 1990.
17. HP. Configuring and using DDR3 memory with HP ProLiant Gen8 Servers, 2012. http://h20000. www2. hp. com/bc/docs/support/ Support-Manual/c03293145/c03293145. pdf.
18. HPC Challenge. GUPS. http://icl. cs. utk. edu/ projectsfiles/hpcc/RandomAccess/.
19. Intel. Intel Extreme Memory Profile (Intel XMP) DDR3 Technology. http://www. intel. com/content/www/us/en/chipsets/ extreme-memory-profile-ddr3-technology-paper. html, 2009.
20. E. Ipek et al. Self-optimizing memory controllers: A reinforcement learning approach. In ISCA, 2008.
21. JEDEC. Application Specific Memory for a Server Centric World. http://www. jedec. org/sites/default/files/ EugeneKim-dcrp. pdf, 2012.
22. JEDEC. DDR4 SDRAM Standard, 2012.
23. JEDEC. Low Power Double Data Rate 3 (LPDDR3), 2012.
24. JEDEC. Standard No. 21C. Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Aug. 2012.
25. JEDEC. Standard No. 79-3F. DDR3 SDRAM Specification, July 2012.
26. U. Kang et al. Co-architecting controllers and DRAM to enhance DRAM process scaling. In The Memory Forum, 2014.
27. B. Keeth and R. J. Baker. DRAM Circuit Design: A Tutorial. Wiley-IEEE Press, 2000.
28. S. Khan et al. Improving Cache Performance by Exploiting Read-Write Disparity. In HPCA, 2014.
29. S. Khan et al. The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study. In SIGMETRICS, 2014.
30. K. Kim and J. Lee. A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs. In EDL, 2009.
31. Y. Kim et al. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA, 2014.
32. Y. Kim et al. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In HPCA, 2010.
33. Y. Kim et al. Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. In MICRO, 2010.
34. Y. Kim et al. A case for exploiting subarray-level parallelism (SALP) in DRAM. In ISCA, 2012.
35. D. Lee et al. Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case. http://www. ece. cmu. edu/safari/ tools/aldram-hpca2015-fulldata. html.
36. D. Lee et al. Tiered-latency DRAM: A low latency and low cost DRAM architecture. In HPCA, 2013.
37. J. Lee et al. Simultaneously Formed Storage Node Contact and Metal Contact Cell (SSMC) for 1Gb DRAM and Beyond. In IEDM, 1996.
38. Y. Li et al. DRAM Yield Analysis and Optimization by a Statistical Design Approach. In IEEE TCSI, 2011.
39. J. Lin et al. Software Thermal Management of DRAM Memory for Multicore Systems. In SIGMETRICS, 2008.
40. J. Lin et al. Thermal Modeling and Management of DRAM Systems. In ISCA, 2007.
41. J. Liu et al. An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms. In ISCA, 2013.
42. J. Liu et al. RAIDR: Retention-Aware Intelligent DRAM Refresh. In ISCA, 2012.
43. S. Liu et al. Hardware/software techniques for DRAM thermal management. In HPCA, 2011.
44. J. D. McCalpin. STREAM: Sustainable Memory Bandwidth in High Performance Computers. Technical report, University of Virginia, 1991-2007.
45. Micron. RLDRAM 2 and 3 Specifications. http://www. micron. com/products/dram/rldram-memory.
46. Micron. Mobile DRAM Power-Saving Features and Power Calculations. http://www. micron. com//media/documents/ products/technical-note/dram/tn4612. pdf, 2005.
47. Micron. DDR3 SDRAM System-Power Calculator, 2010.
48. Y. Mori et al. The origin of variable retention time in DRAM. In IEDM, 2005.
49. T. Moscibroda and O. Mutlu. Memory Performance Attacks: Denial of Memory Service in Multi-core Systems. USENIX Security, 2007.
50. S. P. Muralidhara et al. Reducing memory interference in multicore systems via application-aware memory channel partitioning. In MICRO, 2011.
51. O. Mutlu. Memory Scaling: A Systems Architecture Perspective. In MemCon, 2013.
52. Nvidia. Extreme DDR3 Performance with SLI-Ready Memory. http://www. nvidia. com/docs/IO/52280/NVIDIA EPP2-TB. pdf, 2008.
53. G. Pekhimenko et al. Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency. In PACT, 2012.
54. G. Pekhimenko et al. Base-Delta-Immediate Compression: A Practical Data Compression Mechanism for On-Chip Caches. In PACT, 2012.
55. Rambus. DRAM Power Model. http://www. rambus. com/ energy, 2010.
56. B. Razavi. Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2000.
57. P. J. Restle et al. DRAM variable retention time. In IEDM, 1992.
58. B. M. Rogers et al. Scaling the Bandwidth Wall: Challenges in and Avenues for CMP Scaling. In ISCA, 2009.
59. Samsung. DRAM Data Sheet. http://www. samsung. com/ global/business/semiconductor.
60. S. R. Sarangi et al. Varius: A model of process variation and resulting timing errors for microarchitects. In IEEE Transactions on Semiconductor Manufacturing, 2008.
61. Y. Sato et al. Fast Cycle RAM (FCRAM); a 20-ns random row access, pipe-lined operating DRAM. In Symposium on VLSI Circuits, 1998.
62. V. Seshadri et al. RowClone: Fast and Energy-efficient in-DRAM Bulk Data Copy and Initialization. In MICRO, 2013.
63. V. Seshadri et al. The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing. In PACT, 2012.
64. A. Shafiee et al. MemZip: Exploring Unconventional Benefits from Memory Compression. In HPCA, 2014.
65. W. Shin et al. NUAT: A Non-Uniform Access Time Memory Controller. In HPCA, 2014.
66. Y. H. Son et al. Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations. In ISCA, 2013.
67. S. Srinath et al. Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. In HPCA, 2007.
68. A. J. van de Goor and I. Schanstra. Address and Data Scrambling: Causes and Impact on Memory Tests. In DELTA, 2002.
69. T. Vogelsang. Understanding the Energy Consumption of Dynamic Random Access Memories. In MICRO, 2010.
70. M.-J. Wang et al. Guardband determination for the detection of off-state and junction leakages in DRAM testing. In Asian Test Symposium, 2001.
71. Xilinx. Virtex-6 FPGA Integrated Block for PCI Express, 2011. http://www. xilinx. com/support/documentation/ip documentation/mig/v3-92/ug406. pdf.
72. Xilinx. ML605 Hardware User Guide, Oct. 2012. http: //www. xilinx. com/support/documentation/boards and-kits/ug534. pdf.
73. Xilinx. Virtex-6 FPGA Memory Interface Solutions, 2013. http://www. xilinx. com/support/documentation/ ip-documentation/mig/v3-92/ug406. pdf.
74. D. Yaney et al. A meta-stable leakage phenomenon in DRAM charge storage-Variable hold time. In IEDM, 1987.
75. Z. Zhang et al. Cached DRAM for ILP processor memory access latency reduction. IEEE Micro, July 2001.
76. Q. Zhu et al. Thermal management of high power memory module for server platforms. In ITHERM, 2008.