Fully-buffered DIMM memory architectures: Understanding mechanisms, overheads and scaling

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2007, Pages 109-120

  Ganesh, Brinda ^a   Jaleel, Aamer ^b   Wang, David ^a   Jacob, Bruce ^a  

^a UNIVERSITY OF MARYLAND   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIMM MEMORY ARCHITECTURES; FULLY-BUFFERED DIMM; MEMORY BUS WIDTHS; MEMORY CONTROLLER;

BANDWIDTH; BUFFER STORAGE; INTERFACES (COMPUTER); STORAGE ALLOCATION (COMPUTER);

COMPUTER ARCHITECTURE;

EID: 34547653935     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2007.346190     Document Type: Conference Paper

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