A 60nm 6Gb/s/pin GDDR5 graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 277-279

  Bae, Seung Jun ^a   Sohn, Young Soo ^a   Park, Kwang Il ^a   Kim, Kyoung Ho ^a   Chung, Dae Hyun ^a   Kim, Jin Gook ^a   Kim, Si Hong ^a   Park, Min Sang ^a   Lee, Jae Hyung ^a   Bang, Sam Young ^a   Lee, Ho Kyung ^a   Park, In Soo ^a   Kim, Jae Sung ^a   Kim, Dae Hyun ^a   Kim, Hye Ran ^a   Shin, Yong Jae ^a   Park, Cheol Goo ^a   Moon, Gil Shin ^a   Yeom, Ki Woong ^a   Kim, Kang Young ^a   Lee, Jae Young ^a   Yang, Hyang Ja ^a   Jang, Seong Jin ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a   Kim, Kinam ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

PHASE LOCKED LOOPS;

CLOCKING SCHEMES; DATA BUS; LOCKING CYCLE; OUTPUT DATA;

CLOCKS;

EID: 49549102033     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523165     Document Type: Conference Paper

References (3)

1. J.-D. Ihm, S.-J. Bae, K.-I. Park et al., "An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion," ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2007.
2. V. Stojanovic, A. Ho, B. Garlepp et al., "Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery," IEEE J. of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, Apr. 2005.
3. M. Mansuri and C.-K. Yang, "A Low-Power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation," IEEE J. of Solid-State Circuits, vol. 38, no. 11, pp. 1804-1812, Nov. 2003.