BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling

IEEE Transactions on Parallel and Distributed Systems

Volumn 27, Issue 10, 2016, Pages 3071-3087

  Subramanian, Lavanya ^a,b   Lee, Donghyuk ^a   Seshadri, Vivek ^a   Rastogi, Harsha ^a   Mutlu, Onur ^a  

^a INTEL CORPORATION   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; ECONOMIC AND SOCIAL EFFECTS; HARDWARE; INTERFERENCE SUPPRESSION; MEMORY ARCHITECTURE; RECONFIGURABLE HARDWARE;

DEVELOPED APPLICATIONS; HARDWARE COMPLEXITY; LOW HARDWARE COSTS; MEMORY ACCESS SCHEDULING; MULTI-CORE SYSTEMS; STATE OF THE ART; SYSTEM CONFIGURATIONS; TIMING REQUIREMENTS;

SCHEDULING;

EID: 84987892113     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2016.2526003     Document Type: Article

References (58)

1. K. Nesbit, N. Aggarwal, J. Laudon, and J. E. Smith, "Fair queuing memory systems," in Proc. 39th Annu. IEEE/ACM Int. Symp. Microarchit., 2006, pp. 208-222.
2. T. Moscibroda and O. Mutlu, "Memory performance attacks: Denial of memory service in multi-core systems," in Proc. 16th USENIX Security Symp. USENIX Security Symp., 2007, pp. 18:1-18:18
3. O. Mutlu and T. Moscibroda, "Stall-time fair memory access scheduling for chip multiprocessors," in Proc. 40th Annu. IEEE/ ACM Int. Symp. Microarchit., 2007, pp. 146-160.
4. O. Mutlu and T. Moscibroda, "Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems," in Proc. 35th Annu. Int. Symp. Comput. Archit., 2008, pp. 63-74.
5. T. Moscibroda and O. Mutlu, "Distributed order scheduling and its application to multi-core DRAM controllers," in Proc. 27th ACM Symp. Principles Distrib. Comput., 2008, pp. 365-374.
6. Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter, "ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers," in Proc. IEEE 16th Int. Symp. High Perform. Comput. Archit., 2010, pp. 1-12.
7. Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter, "Thread cluster memory scheduling: exploiting differences in memory access behavior," in Proc. 43rd Annu. IEEE/ACM Int. Symp. Microarchit., 2010, pp. 65-76.
8. S. Ghose, H. Lee, and J. F. Martínez, "Improving memory scheduling via processor-side load criticality information," in Proc. 40th Annu. Int. Symp. Comput. Archit., 2013, pp. 84-95.
9. S. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, and T. Moscibroda, "Reducing memory interference in multicore systems via Application-aware memory channel partitioning," in Proc. 44th Annu. IEEE/ACM Int. Symp. Microarchit., 2011, pp. 374-385.
10. D. Kaseridis, J. Stuecheli, and L. K. John, "Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era," in Proc. 44th Annu. IEEE/ACM Int. Symp. Microarchit., 2011, pp. 24-35.
11. E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt, "Fairness via source throttling: A configurable and high-performance fairness substrate for multi-core memory systems," in Proc. 15th Ed. ASPLOS Archit. Support Program. Lang. Oper. Syst., 2010, pp. 335-346.
12. L. Subramanian, V. Seshadri, Y. Kim, B. Jaiyen, and O. Mutlu, "MISE: Providing performance predictability and improving fairness in shared main memory systems," in Proc. IEEE 19th Int. Symp. High Perform. Comput. Archit., 2013, pp. 639-650.
13. L. Subramanian, V. Seshadri, A. Ghosh, S. Khan, and O. Mutlu, "The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory," in Proc. 48th Int. Symp. Microarchit., 2015, pp. 62-75.
14. H. Kim, D. D. Niz, B. Andersson, M. Klien, O. Mutlu, and R. Rajkumar, "Bounding memory interference delay in COTS-based multi-core systems," in Proc. Real-Time Embedded Technol. Appl. Symp., 2014, pp. 145-154.
15. L. Tang, J. Mars, N. Vachharajani, R. Hundt, and M. L. Soffa, "The impact of memory subsystem resource sharing on datacenter applications," in Proc. 38th Annu. Int. Symp. Comput. Archit., 2011, pp. 283-294.
16. S. Zhuravlev, S. Blagodurov, and A. Fedorova, "Addressing shared resource contention in multicore processors via scheduling," in Proc. 15th Ed. ASPLOS Archit. Support Program. Lang. Oper. Syst., 2010, pp. 129-142.
17. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, "Memory access scheduling," in Proc. 27th Annu. Int. Symp. Comput. Archit., 2000, pp. 128-138.
18. JEDEC, Standard No. 79-3. DDR3 SDRAM STANDARD, 2010.
19. Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," in Proc. 39th Annu. Int. Symp. Comput. Archit., 2012, pp. 368-379.
20. D. Lee, Y. Kim, V. Seshadri, J. Liu, L. Subramanian, and O. Mutlu, "Tiered-latency DRAM: A low latency and low cost DRAM architecture," in Proc. IEEE 19th Int. Symp. High Perform. Comput. Archit., 2013, pp. 615-626.
21. D. Lee, K. Yoongu, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu, "Adaptive-latency DRAM: Optimizing DRAM timing for the common-case," in Proc. IEEE 21st Int. Symp. High Perform. Comput. Archit., 2015, pp. 489-501.
22. V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. Gibbons, M. Kozuch, and T. Mowry, "RowClone: Fast and efficient In-DRAM copy and initialization of bulk data," in Proc. 46th Annu. IEEE/ACM Int. Symp. Microarchit., 2013, pp. 185-197.
23. W. Zuravleff and T. Robinson, "Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order," Patent 5 630 096, 1997.
24. SPEC. (2006). SPEC CPU2006 [Online]. Available: http://www. spec.org/spec2006
25. Y. Kim, W. Yang, and O. Mutlu, "Ramulator: A fast and extensible DRAM simulator," IEEE Comput. Archit. Lett., vol. PP, no. 99, pp. 1-1, 2015.
26. CMU SAFARI Research Group. (2015). Ramulator [Online]. Available: https://github.com/CMU-SAFARI/ramulator
27. C. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood, "Pin: Building customized program analysis tools with dynamic instrumentation," in Proc. ACM SIGPLAN Conf. Program. Lang. Des. Implementation, 2005, pp. 190-200.
28. CMU SAFARI Research Group. (2015). MemSchedSim [Online]. Available: https://github.com/CMU-SAFARI/MemSchedSim
29. Micron, "2Gb: x4, x8, x16, DDR3 SDRAM," 2012.
30. NASA advanced supercomputing division, NAS Parallel Benchmark Suite [Online]. Available: https://www.nas.nasa.gov/publications/ npb.html.
31. R. Das, O. Mutlu, T. Moscibroda, and C. Das, "Applicationaware prioritization mechanisms for on-chip networks," in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchit., 2009, pp. 280-291.
32. S. Eyerman and L. Eeckhout, "System-level performance metrics for multiprogram workloads," IEEE Micro, vol. 28, no. 3, pp. 42-53, May/Jun. 2008.
33. A. Snavely and D. M. Tullsen, "Symbiotic jobscheduling for a simultaneous multithreaded processor," in Proc. 9th Int. Conf. Archit. Support Program. Lang. Oper. Syst., 2000, pp. 234-244.
34. H. Vandierendonck and A. Seznec, "Fairness metrics for multithreaded processors," IEEE Comput. Archit. Lett., vol. 10, no. 1, pp. 4-7, Jan. 2011.
35. K. Luo, J. Gummaraju, and M. Franklin, "Balancing thoughput and fairness in SMT processors," in Proc. IEEE Int. Symp. Perform. Anal. Syst. Softw., 2001, pp. 164-171.
36. V. Seshadri, O. Mutlu, M. A. Kozuch, and T. C. Mowry, "The evicted-address filter: A unified mechanism to address both cache pollution and thrashing," in Proc. 21st Int. Conf. Parallel Archit. Compilation Techn., 2012, pp. 355-366.
37. JEDEC, Standard No. 79-4. DDR4 SDRAM STANDARD, 2012.
38. S. Srinath, O. Mutlu, H. Kim, and Y. N. Patt, "Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers," in Proc. IEEE 13th Int. Symp. High Perform. Comput. Archit., 2007, pp. 63-74.
39. E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt, "Prefetchaware shared resource management for multi-core systems," in Proc. 38th Annu. Int. Symp. Comput. Archit., 2011, pp. 141-152.
40. E. Ebrahimi, O. Mutlu, C. J. Lee, and Y. N. Patt, "Coordinated control of multiple prefetchers in multi-core systems," in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchit., 2009, pp. 316-326.
41. E. Ebrahimi, R. Miftakhutdinov, C. Fallin, C. J. Lee, J. A. Joao, O. Mutlu, and Y. N. Patt, "Parallel application memory scheduling," in Proc. 44th Annu. IEEE/ACM Int. Symp. Microarchit., 2011, pp. 362-373.
42. R. Ausavarungnirun, K. Chang, L. Subramanian, G. H. Loh, and O. Mutlu, "Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems," in Proc. 39th Annu. Int. Symp. Comput. Archit., 2012, pp. 416-427.
43. H. Usui, L. Subramanian, K. Chang, and O. Mutlu, "DASH: Deadline-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators," ACM Trans. Archit. Code. Optim., vol. 12, no. 3, pp. 65:1-65:28, Jan. 2016.
44. J. Zhao, O. Mutlu, and Y. Xie, "FIRM: Fair and high-performance memory control for persistent memory systems," in Proc. 47th Annu. IEEE/ACM Int. Symp. Microarchit., 2014, pp. 153-165.
45. G. Yuan, A. Bakhoda, and T. M. Aamodt, "Complexity effective memory access scheduling for many-core accelerator architectures," in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchit., 2009, pp. 34-44.
46. M. Jeong, D. H. Yoon, D. Sunwoo, M. Sullivan, I. Lee, and M. Erez, "Balancing DRAM locality and parallelism in shared memory CMP systems," in Proc. IEEE 18th Int. Symp. High Perform. Comput. Archit., 2012, pp. 1-12.
47. L. Liu, Z. Cui, M. Xing, Y. Bao, M. Chen, and C. Wu, "A software memory partition approach for eliminating bank-level interference in multicore systems," in Proc. 21st Int. Conf. Parallel Archit. Compilation Techn., 2012, pp. 367-376.
48. M. Xie, D. Tong, K. Huang, and X. Cheng, "Improving system throughput and fairness simultaneously in shared memory CMP systems via dynamic bank partitioning," in Proc. IEEE 20th Int. Symp. High Perform. Comput. Archit., 2014, pp. 344-355.
49. M. Thottethodi, A. Lebeck, and S. Mukherjee, "Self-tuned congestion control for multiprocessor networks," in Proc. 7th Int. Symp. High-Perform. Comput. Archit., 2001, p. 107.
50. E. Baydal, P. Lopez, and J. Duato, "A family of mechanisms for congestion control in wormhole networks," IEEE Trans. Parallel Distrib. Syst., vol. 16, no. 9, pp. 772-784, Sep. 2005.
51. K. Chang, R. Ausavarungnirun, C. Fallin, and O. Mutlu, "HAT: Heterogeneous adaptive throttling for on-chip networks," in Proc. IEEE Int. Symp. Comput. Archit. High Perform. Comput., 2012, pp. 9-18.
52. R. Ausavarungnirun, C. Fallin, X. Yu, K. Chang, G. Nazario, R. Das, G. Loh, and O. Mutlu, "Design and evaluation of hierarchical rings with deflection routing," in Proc. IEEE 26th Int. Symp. Comput. Archit. High Perform. Comput., 2014, pp. 230-237.
53. G. Nychis, C. Fallin, T. Moscibroda, and O. Mutlu, "On-chip networks from a networking perspective: Congestion and scalability in many-core interconnects," in Proc. ACM SIGCOMM Conf. Appl., Technol., Archit. Protocols Comput. Commun., 2012, pp. 407-418.
54. G. Nychis, C. Fallin, T. Moscibroda, and O. Mutlu, "Next generation on-chip networks: What kind of congestion control do we need?" in Proc. 9th ACM SIGCOMM Workshop Hot Topics Netw., 2010, pp. 12:1-12:6.
55. O. Kayiran, N. C. Nachiappan, A. Jog, R. Ausavarungnirun, M. T. Kandemir, G. H. Loh, O. Mutlu, and C. R. Das, "Managing GPU concurrency in heterogeneous architectures," in Proc. 47th Annu. IEEE/ACM Int. Symp. Microarchit., 2014, pp. 114-126.
56. R. Das, R. Ausavarungnirun, O. Mutlu, A. Kumar, and M. Azimi, "Application-to-core mapping policies to reduce memory system interference in multi-core systems," in Proc. IEEE 19th Int. Symp. High Perform. Comput. Archit., 2013, pp. 107-118.
57. H. Wang, C. Isci, L. Subramanian, J. Choi, D. Qian, and O. Mutlu, "A-DRM: Architecture-aware distributed resource management of virtualized clusters," in Proc. 11th ACM SIGPLAN/SIGOPS Int. Conf. Virtual Execution Environ., 2015, pp. 93-106.
58. L. Subramanian, D. Lee, V. Seshadri, H. Rastogi, and O. Mutlu, "The blacklisting memory scheduler: Achieving high performance and fairness at low cost," in Proc. 32nd IEEE Int. Conf. Comput. Des., 2014, pp. 8-15.