Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2014, Pages 344-355

  Xie, Mingli ^a   Tong, Dong ^a   Huang, Kan ^a   Cheng, Xu ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTERFERENCE SUPPRESSION; SCHEDULING; SUPERCOMPUTERS;

IMPROVING SYSTEMS; MEMORY ACCESS SCHEDULING; MEMORY CHANNELS; MEMORY CONTENTIONS; MEMORY PARTITIONING; MEMORY RESOURCES; SHARED MEMORY; SYSTEM THROUGHPUT;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84904016025     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2014.6835945     Document Type: Conference Paper

References (31)

1. Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers. HPCA, 2010.
2. Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter. Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. MICRO, 2010.
3. O. Mutlu and T. Moscibroda. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. MICRO, 2007.
4. O. Mutlu and T. Moscibroda. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. ISCA, 2008.
5. K. Nesbit, N. Aggarwal, J. Laudon, and J. Smith. Fair Queuing Memory Systems. MICRO, 2006.
6. N. Rafique, W.-T. Lim, and M. Thottethodi. Effective Management of DRAM Bandwidth in Multicore Processors. PACT, 2007.
7. M. Jeong, D. Yoon, D. Sunwoo, M. Sullivan, I. Lee, and M. Erez. Balancing DRAM Locality and Parallelism in Shared Memory CMP Systems. HPCA, 2012.
8. S. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, and T. Moscibroda. Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning. MICRO, 2011.
9. R. Ausavarungnirun, K. Chang, L. Subramanian, G. Loh, and O. Mutlu. Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems. ISCA, 2012.
10. Micron Technology, Inc. Micron DDR3 SDRAM Part MT41J256M8, 2006.
11. H. Park, S. Baek, J. Choi, D. Lee, and S. Noh. Regularities Considered Harmful: Forcing Randomness to Memory Accesses to Reduce Row Buffer Conflicts for Multi-Core, Multi-Bank Systems. ASPLOS, 2013.
12. B. Jacob, S. W. Ng, and D. T. Wang. Memory Systems: Cache, DRAM, Disk. Elsevier, 2008.
13. P. Rosenfeld, E. Cooper-Balis, and B. Jacob. DRAMSim2: A Cycle Accurate Memory System Simulator. IEEE CAL, vol. 10, pages 16-19, 2011.
14. N. Binkert, B. Beckmann, G. Black, S. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. Hill, and D. Wood. The Gem5 Simulator. SIGARCH CAN, vol. 39, pages 1-7, 2011.
15. W. Mi, X. Feng, J. Xue, and Y. Jia. Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors. NPC, 2010.
16. L. Liu, Z. Cui, M. Xing, Y. Bao, M. Chen, and C. Wu. A Software Memory Partition Approach for Eliminating Bank-level Interference in Multicore Systems. PACT, 2012.
17. H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu. Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency. MICRO, 2008.
18. J. L. Henning. SPEC CPU2006 Memory Footprint. ACM SIGARCH Computer Architecture News, 2007.
19. L. Subramanian, V. Seshadri, Y. Kim, B. Jaiyen, and O. Mutlu. MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems. HPCA, 2013.
20. H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. Memory Access Scheduling Schemes for Systems with Multi-core Processors. ICPP, 2008.
21. I. Hur and C. Lin. Adaptive History-based Memory Schedulers. MICRO, 2004.
22. S. A. McKee, W. A. Wulf, J. Aylor, R. Klenke, M. Salinas, S. Hong, and D. Weikle. Dynamic Access Ordering for Streamed Computations. IEEE TC, vol. 49, pages 1255-1271, Nov. 2000.
23. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory Access Scheduling. ISCA, 2000.
24. J. Shao and B. T. Davis. A Burst Scheduling Access Reordering Mechanism. HPCA, 2007.
25. C. Natarajan, B. Christenson, and F. Briggs. A Study of Performance Impact of Memory Controller Features in Multi-processor Server Environment. WMPI, 2004.
26. W. K. Zuravle and T. Robinson. Controller for a Synchronous DRAM that Maximizes Throughput by Allowing Memory Requests and Commands to be Issued Out of Order. U.S. Patent Number 5, 630, 096, May 1997.
27. M. Awasthi, D. Nellans, K. Sudan, R. Balasubramonian, and A. Davis. Handling the Problems and Opportunities Posed by Multiple on-chip Memory Controllers. PACT, 2010.
28. SPEC CPU2006. http://www.spec.org/spec2006.
29. M. Xie, D. Tong, Y. Feng, K. Huang, X. Cheng. Page Policy Control with Memory Partitioning for DRAM Performance and Power Efficiency. ISLPED, 2013.
30. T. Karkhanis and J. E. Smith. A Day in the Life of a Data Cache Miss. WMPI, 2002.
31. H. Cheng, C. Lin, J. Li, and C. Yang. Memory Latency Reduction via Thread Throttling. MICRO, 2010.