Tiered-latency DRAM: A low latency and low cost DRAM architecture

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 615-626

  Lee, Donghyuk ^a   Kim, Yoongu ^a   Seshadri, Vivek ^a   Liu, Jamie ^a   Subramanian, Lavanya ^a   Mutlu, Onur ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; AREA OVERHEAD; BITLINE CAPACITANCE; COMPLEX COMPUTER SYSTEMS; MEMORY LATENCIES; PARASITIC CAPACITANCE; PERFORMANCE BOTTLENECKS; SENSE AMPLIFIER;

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS; COSTS; SUPERCOMPUTERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84880276949     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522354     Document Type: Conference Paper

References (60)

1. STREAM Benchmark. http://www.streambench.org/.
2. J. H. Ahn et al. Multicore DIMM: an energy eXcient memory module with independently controlled DRAMs. IEEE CAL, January 2009.
3. J. H. Ahn et al. Improving system energy eXciency with memory rank subsetting. ACM TACO, Mar. 2012.
4. R. Ausavarungnirun et al. Staged memory scheduling: achieving high performance and scalability in heterogeneous systems. In ISCA, 2012.
5. S. Borkar and A. A. Chien. The future of microprocessors. In CACM, 2011.
6. D. Burns et al. An RLDRAM II Implementation of a 10Gbps Shared Packet BuUer for Network Processing. In AHS, 2007.
7. R. Chandra et al. Scheduling and page migration for multiprocessor compute servers. In ASPLOS, 1994.
8. J. Collins and D. M. Tullsen. Hardware identiVcation of cache conWict misses. In MICRO, 1999.
9. E. Ebrahimi et al. Parallel application memory scheduling. In MICRO, 2011.
10. Enhanced Memory Systems. Enhanced SDRAM SM2604, 2002.
11. K. Ghose and M. B. Kamble. Reducing power in superscalar processor caches using subbanking, multiple line buUers and bit-line segmentation. In ISLPED, 1999.
12. C. A. Hart. CDRAM in a uniVed memory architecture. In Compcon Spring '94, Digest of Papers, 1994.
13. H. Hidaka et al. The cache DRAM architecture: A DRAM with an on-chip cache memory. IEEE Micro, March 1990.
14. HPC Challenge. GUPS. http://icl.cs.utk.edu/projectsfiles/hpcc/ RandomAccess/.
15. W.-C. Hsu and J. E. Smith. Performance of cached DRAM organizations in vector supercomputers. In ISCA, 1993.
16. ITRS. International Technology Roadmap for Semiconductors: Process Integration, Devices, and Structures. http://www.itrs.net/Links/2007ITRS/ Home2007.htm, 2007.
17. A. Jaleel et al. High performance cache replacement using re-reference interval prediction. In ISCA, 2010.
18. T. Johnson et al. Run-time cache bypassing. IEEE TC, 1999.
19. T. S. Jung. Memory technology and solutions roadmap. http://www.sec.co. kr/images/corp/ir/irevent/techforum-01.pdf, 2005.
20. G. Kedem and R. P. Koganti. WCDRAM: A fully associative integrated cached-DRAM with wide cache lines. Duke, (CS-1997-03), 1997.
21. B. Keeth et al. DRAM Circuit Design. Fundamental and High-Speed Topics. Wiley-IEEE Press, 2007.
22. Y. Kim et al. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In HPCA, 2010.
23. Y. Kim et al. Thread cluster memory scheduling: Exploiting diUerences in memory access behavior. In MICRO, 2010.
24. Y. Kim et al. A case for exploiting subarray-level parallelism (SALP) in DRAM. In ISCA, 2012.
25. T. Kimura et al. 64Mb 6.8ns random row access DRAM macro for ASICs. In ISSCC, 1999.
26. C.-K. Luk et al. Pin: building customized program analysis tools with dynamic instrumentation. In PLDI, 2005.
27. Micron. RLDRAM 2 and 3 SpeciVcations. http://www.micron.com/products/ dram/rldram-memory.
28. Micron. Verilog: DDR3 SDRAM Verilog model. http://www. micron.com/get-document/?documentId=808.
29. Micron. DDR3 SDRAM System-Power Calculator, 2010.
30. Y. Moon et al. 1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense ampliVer and segmented sub-array architecture. ISSCC, 2009.
31. O. Mutlu and T. Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In MICRO, 2007.
32. O. Mutlu and T. Moscibroda. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In ISCA, 2008.
33. S. Narasimha et al. High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography. In IEDM, 2006.
34. NEC. Virtual Channel SDRAM uPD4565421, 1999.
35. D. A. Patterson. Latency lags bandwith. Commun. ACM, Oct. 2004.
36. T. Piquet et al. Exploiting single-usage for eUective memory management. In ACSAC, 2007.
37. M. K. Qureshi et al. Adaptive insertion policies for high performance caching. In ISCA, 2007.
38. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO, 2006.
39. Rambus. DRAM Power Model. http://www.rambus.com/energy, 2010.
40. R. Rao et al. Exploiting non-uniform memory access patterns through bitline segmentation. In WMPI, 2006.
41. S. Rixner et al. Memory access scheduling. In ISCA, 2000.
42. P. Rosenfeld et al. DRAMSim2: A cycle accurate memory system simulator. IEEE CAL, January 2011.
43. Samsung. DRAM Data Sheet. http://www.samsung.com/global/business/ semiconductor/product.
44. R. H. Sartore et al. Enhanced DRAM with embedded registers. U.S. patent, 1999. Patent number 5887272.
45. Y. Sato et al. Fast Cycle RAM (FCRAM); a 20-ns random row access, pipe-lined operating DRAM. In Symposium on VLSI Circuits, 1998.
46. V. Seshadri et al. The Evicted-Address Filter: A uniVed mechanism to address both cache pollution and thrashing. In PACT, 2012.
47. S. M. Sharroush et al. Dynamic random-access memories without sense ampliVers. In Elektrotechnik & Informationstechnik, 2012.
48. J. M. Sibigtroth et al. Memory bit line segment isolation. U.S. patent, 2006. Patent number 7042765.
49. A. Snavely and D. M. Tullsen. Symbiotic jobscheduling for a simultaneous multithreaded processor. In ASPLOS, 2000.
50. K. Sudan et al. Micro-pages: Increasing DRAM eXciency with localityaware data placement. In ASPLOS, 2010.
51. S. Thoziyoor et al. A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. In ISCA, 2008.
52. Transaction Processing Performance Council. http://www.tpc. org/.
53. B. Verghese et al. Operating system support for improving data locality on cc-numa compute servers. In ASPLOS, 1996.
54. T. Vogelsang. Understanding the energy consumption of dynamic random access memories. In MICRO, 2010.
55. F. Ware and C. Hampel. Improving power and data eXciency with threaded memory modules. In ICCD, 2006.
56. M. V. Wilkes. The memory gap and the future of high performance memories. SIGARCH Comput. Archit. News, March 2001.
57. W. A. Wong and J.-L. Baer. DRAM caching. Technical Report UW-CSE-97-03-04, 1997.
58. W. A. Wulf and S. A. McKee. Hitting the memory wall: implications of the obvious. SIGARCH Comput. Archit. News, March 1995.
59. Z. Zhang et al. Cached DRAM for ILP processor memory access latency reduction. IEEE Micro, July 2001.
60. H. Zheng et al. Mini-rank: Adaptive DRAM architecture for improving memory power eXciency. In MICRO, 2008.