Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 416-427

  Ausavarungnirun, Rachata ^a   Chang, Kevin Kai Wei ^a   Subramanian, Lavanya ^a   Loh, Gabriel H ^b   Mutlu, Onur ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX HARDWARE; CPU CORES; DESIGN TRADEOFF; FIFO QUEUE; FRAME RATE; HETEROGENEOUS SYSTEMS; HIGH LEVEL POLICIES; HIGH-PERFORMANCE AND SCALABILITIES; LAST STAGE; MAIN MEMORY; MEMORY CONTROLLER; MEMORY SCHEDULING; MULTIPLE PROCESSORS; OFF-CHIP; PRIMARY TASK; REQUEST SCHEDULING; SYSTEM SOFTWARES;

COMPUTER ARCHITECTURE; HARDWARE; SCHEDULING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84864843567     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237036     Document Type: Conference Paper

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