Prefetch-aware shared-resource management for multi-core systems

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 141-152

  Ebrahimi, Eiman ^a   Lee, Chang Joo ^a,b   Mutlu, Onur ^c   Patt, Yale N ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INTEL CORPORATION   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Fairness; Multi core; Prefetching; Shared resources

Indexed keywords

BATCH-SCHEDULING; CHIP MULTIPROCESSOR; EXISTING SYSTEMS; FAIR QUEUING; FAIRNESS; MANAGEMENT TECHNIQUES; MEMORY SCHEDULING; MEMORY SUBSYSTEMS; MULTI CORE; MULTI-CORE SYSTEMS; MULTICORE CHIPS; PREFETCHES; PREFETCHING; SHARED MEMORY SYSTEM; SHARED RESOURCES;

INDUSTRIAL MANAGEMENT; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; NATURAL RESOURCES MANAGEMENT; NETWORK ARCHITECTURE; OCCUPATIONAL RISKS; RESOURCE ALLOCATION; SCHEDULING; SCHEDULING ALGORITHMS;

COMPUTER RESOURCE MANAGEMENT; MICROPROCESSOR CHIPS;

EID: 80052522711     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000081     Document Type: Conference Paper

References (39)

1. J. Baer and T. Chen. An effective on-chip preloading scheme to reduce data access penalty. In Proceedings of Supercomputing '91, 1991.
2. J. Casazza. First the Tick, Now the Tock: Intel Microarchitecture (Nehalem)-White Paper. Intel, 2009.
3. R. Das et al. Application-aware prioritization mechanisms for on-chip networks. In MICRO-42, 2009.
4. R. Das et al. Aergia: Exploiting packet latency slack in on-chip networks. In ISCA-37, 2010.
5. J. Doweck. Inside Intel Core Microarchitecture and Smart Memory Access-White Paper. Intel.
6. E. Ebrahimi et al. Coordinated control of multiple prefetchers in multi-core systems. In MICRO-42, 2009.
7. E. Ebrahimi et al. Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. In HPCA-15, 2009.
8. E. Ebrahimi et al. Fairness via source throttling: A configrable and high-performance fairness substrate for multi-core memory systems. In ASPLOS-XV, 2010.
9. E. Ebrahimi et al. Prefetch-aware shared-resource management for multi-core systems. Technical Report TR4HPS2010-005, The University of Texas at Austin, 2010.
10. R. Gabor et al. Fairness and throughput in switch on even multithreading. In MICRO-39, 2006.
11. B. Grot et al. Preemptive virtual clock: A flexible, efficient, and cost-effective QoS scheme for networks-on-a-chip. In MICRO-42, 2009.
12. L. R. Hsu et al. Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. In PACT-15, 2006.
13. R. Iyer et al. QoS policies and architecture for cache/memory in CMP platforms. In SIGMETRICS '07.
14. S. Kim et al. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT-13, 2004.
15. Y. Kim et al. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In HPCA-16, 2010.
16. Y. Kim et al. Thread cluster memory scheduling: Exploiting differences in memory access behavior. In MICRO-43, 2010.
17. H. Q. Le et al. IBM POWER6 microarchitecture. IBM Journal of Research and Development, 51:639-662, 2007.
18. C. J. Lee et al. Prefetch-aware DRAM controllers. In MICRO-41, 2008.
19. C. J. Lee et al. Improving memory bank-level parallelism in the presence of prefetching. In MICRO-42, 2009.
20. J. W. Lee et al. Globally-synchronized frames for guaranteed quality-of-service in on-chip networks. In ISCA-35, 2008.
21. W.-F. Lin et al. Filtering superfluous prefetches using density vectors. In ICCD, 2001.
22. K. Luo et al. Balancing throughput and fairness in SMT processors. In ISPASS, 2001.
23. Micron. Datasheet: 2Gb DDR3 SDRAM, MT41J512M4-64 Meg x4 x 8 banks, http://download.micron.com/pdf/datasheets/dram/ddr3.
24. T. Moscibroda and O. Mutlu. Memory performance attacks: Denial of memory service in multi-core systems. In USENIX Security, 2007.
25. O. Mutlu and T. Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In MICRO-40, 2007.
26. O. Mutlu and T. Moscibroda. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In ISCA-35, 2008.
27. K. J. Nesbit et al. Virtual private caches. In ISCA-34.
28. K. J. Nesbit et al. AC/DC: An adaptive data cache prefetcher. In PACT-13, 2004.
29. K. J. Nesbit et al. Fair queuing memory systems. In MICRO-39, 2006.
30. J. Owen and M. Steinman. Northbridge architecture of AMD's Griffin microprocessor family. IEEE Micro, 28(2), 2008.
31. H. Patil et al. Pinpointing representative portions of large Intel Itanium programs with dynamic instrumentation. In MICRO-37, 2004.
32. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO-39, 2006.
33. N. Rafique et al. Architectural support for operating system-driven CMP cache management. In PACT-15, 2006.
34. S. Rixner et al. Memory access scheduling. In ISCA-27, 2000.
35. A. Snavely and D. M. Tullsen. Symbiotic job scheduling for a simultaneous multithreading processor. In ASPLOS-IX, 2000.
36. S. Srinath et al. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers. In HPCA-13, 2007.
37. V. Srinivasan et al. A static filter for reducing prefetch traffic. Technical Report CSE-TR400-99, University of Michigan, 1999.
38. J. Tendler et al. POWER4 system microarchitecture. IBM Technical White Paper, 2001.
39. X. Zhuang and H.-H. S. Lee. A hardware-based cache pollution filtering mechanism for aggressive prefetches. In ICPP-32, 2003.