A case for exploiting subarray-level parallelism (SALP) in DRAM

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 368-379

  Kim, Yoongu ^a   Seshadri, Vivek ^a   Lee, Donghyuk ^a   Liu, Jamie ^a   Mutlu, Onur ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; AREA OVERHEAD; LOW COST APPROACH; MULTI-CORE SYSTEMS; NEW MECHANISMS; OFF-CHIP MEMORIES; REQUEST SCHEDULING; SUB-ARRAYS; SYSTEM COSTS; TIMING PARAMETERS;

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84864850807     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237032     Document Type: Conference Paper

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