MISE: Providing performance predictability and improving fairness in shared main memory systems

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 639-650

  Subramanian, Lavanya ^a   Seshadri, Vivek ^a   Kim, Yoongu ^a   Jaiyen, Ben ^a   Mutlu, Onur ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ESTIMATION SCHEMES; MAIN MEMORY; MULTI-CORE SYSTEMS; PERFORMANCE DEGRADATION;

COMPUTER ARCHITECTURE; QUALITY OF SERVICE; SUPERCOMPUTERS;

ESTIMATION;

EID: 84880311561     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522356     Document Type: Conference Paper

References (37)

1. SPEC CPU2006. http://www.spec.org/spec2006.
2. R. Ausavarungnirun et al. Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. In ISCA, 2012.
3. F. J. Cazorla et al. Predictable performance in SMT processors: Synergy between the OS and SMTs. IEEE TC, Jul. 2006.
4. R. Das et al. Application-aware prioritization mechanisms for on-chip networks. In MICRO, 2009.
5. K. Du Bois et al. Per-thread cycle accounting in multicore processors. In HiPEAC, 2013.
6. E. Ebrahimi et al. Fairness via source throttling: A configurable and highperformance fairness substrate for multi-core memory systems. In ASPLOS, 2010.
7. E. Ebrahimi et al. Parallel application memory scheduling. In MICRO, 201l.
8. S. Eyerman and L. Eeckhout. Per-thread cycle accounting in SMT processors. In ASPLOS, 2009.
9. S. Eyerman et al. A performance counter architecture for computing accurate CPI components. In ASPLOS, 2006.
10. S. Eyerman et al. A mechanistic performance model for superscalar outof-order processors. ACM TOCS, May 2009.
11. A. Herdrich et al. Rate-based QoS techniques for cache/memory in CMP platforms. In ICS, 2009.
12. Intel. First the tick, now the tock: Next generation Intel microarchitecure (Nehalem). Intel Technical White Paper, 2008.
13. E. Ipek et al. SeIf-optimizing memory controllers: A reinforcement learning approach. In ISCA, 2008.
14. R. Iyer. CQoS: A framework for enabling QoS in shared caches of CMP platforms. In ICS, 2004.
15. R. Iyer et al. QoS policies and architecture for cache/memory in CMP platforms. In SIGMETRlCS, 2007.
16. M. K. Jeong et al. Balancing DRAM locality and parallelism in shared memory CMP systems. In HPCA, 2012.
17. T. S. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA, 2004.
18. D. Kaseridis et al. Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era. In MICRO, 201l.
19. Y. Kim et al. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In HPCA, 2010.
20. Y. Kim et al. Thread cluster memory scheduling: Exploiting differences in memory access behavior. In MICRO, 2010.
21. C.-K. Luk et al. Pin: Building customized program analysis tools with dynamic instrumentation. In PLDI, 2005.
22. K. Luo et al. Balancing thoughput and fairness in SMT processors. In ISPASS, 200 l .
23. C. Luque e t al. CPU accounting i n CMP processors. IEEE CAL, Jan.-Jun. 2009.
24. J. Mars et al. Bubble-Up: Increasing utilization in modern warehouse scale computers via sensible co-Iocations. In MICRO, 201l.
25. Micron. 4Gb DDR3 SDRAM.
26. T. Moscibroda and O. Mutlu. Memory performance attacks: Denial of memory service in multi-core systems. In USENIX Security, 2007.
27. S. P. Muralidhara et al. Reducing memory interference in multicore systems via application-aware memory channel partitioning. In MICRO, 201l.
28. O. Mutlu and T. Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In MICRO, 2007.
29. O. Mutlu and T. Moscibroda. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In ISCA, 2008.
30. K. J. Nesbit et al. Fair queuing memory systems. In MICRO, 2006.
31. H. Patil et al. Pinpointing representative portions of large Intel ltanium programs with dynamic instrumentation. In MICRO-37, 2004.
32. D. Petrou et al. Implementing lottery scheduling: Matching the specializations in traditional schedulers. In USENIX ATEC, 1999.
33. S. Rixner et al. Memory access scheduling. In ISCA, 2000.
34. A. Snavely and D. M. Tullsen. Symbiotic jobscheduling for a simultaneous multithreaded processor. In ASPLOS, 2000.
35. K. Van Craeynest et al. Scheduling heterogeneous multi-cores through performance impact estimation (PIE). In ISCA, 2012.
36. C. A. Waldspurger and W. E. Weihl. Lottery scheduling: Flexible proportional-share resource management. In OSDI, 1994.
37. W. K. Zuravleff and T. Robinson. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order. Patent 5630096, 1997.