-
3
-
-
0005389025
-
Reconfigurable architectures for general purpose computing
-
MIT Artificial Intelligence Laboratory, Sept
-
De Hon, A.: Reconfigurable architectures for general purpose computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory (Sept 1996)
-
(1996)
AI Technical Report
-
-
De Hon, A.1
-
4
-
-
0032681919
-
Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)
-
Monterey, CA, Feb
-
De Hon, A.: Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization). In: International Symposium on Field Programmable Array FPGA, Monterey, CA, pp. 69-78 (Feb. 1999)
-
(1999)
International Symposium on Field Programmable Array FPGA
, pp. 69-78
-
-
De Hon, A.1
-
6
-
-
0021784846
-
A procedure for placement of standard-cell VLSI circuits
-
Jan
-
Dunlop, A., Kernighan, B.: A procedure for placement of standard-cell VLSI circuits. IEEE Trans. CAD, pp. 92-98 (Jan 1985)
-
(1985)
IEEE Trans. CAD
, pp. 92-98
-
-
Dunlop, A.1
Kernighan, B.2
-
9
-
-
85032416817
-
-
Alliance: http://www-asim.lip6.fr/recherche/alliance/(2006)
-
(2006)
-
-
Alliance1
-
11
-
-
85032416009
-
-
Altera: http://www.altera.com (2010)
-
(2010)
-
-
Altera1
-
13
-
-
85032418991
-
-
Altera: Altera. http://www.altera.com (2010)
-
(2010)
Altera
-
-
Altera1
-
14
-
-
0032659075
-
Using cluster-based logic block and timing-driven packing to improve FPGA speed and density
-
Monterey
-
Marquart, A., Betz, V., Rose, J.: Using cluster-based logic block and timing-driven packing to improve FPGA speed and density. In: International Symposium on FPGA, Monterey, pp. 37-46 (1999)
-
(1999)
International Symposium on FPGA
, pp. 37-46
-
-
Marquart, A.1
Betz, V.2
Rose, J.3
-
18
-
-
85032411788
-
-
ATMEL: http://www.atmel.com (2010)
-
(2010)
-
-
ATMEL1
-
19
-
-
33745868036
-
Embedded floating-point units in FPGAs
-
Beauchamp, M., Hauck, S., Underwood, K., Hemmert, K.: Embedded floating-point units in FPGAs. In: FPGA, pp. 12-20 (2006)
-
(2006)
FPGA
, pp. 12-20
-
-
Beauchamp, M.1
Hauck, S.2
Underwood, K.3
Hemmert, K.4
-
22
-
-
0003793410
-
-
Kluwer Academic Publishers, New York Jan
-
Betz, V., Marquardt, A., Rose, J.: Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, New York (Jan 1999)
-
(1999)
Architecture and CAD for Deep-submicron FPGAs
-
-
Betz, V.1
Marquardt, A.2
Rose, J.3
-
23
-
-
0026944167
-
Avery-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements
-
Birkner, J., Chan, A., Chua, H., Chao, A., Gordon, K., Kleinman, B., Kolze, P., Wong, R.: Avery-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements. Microelectron. J. 23(7), 561-568 (1992)
-
(1992)
Microelectron. J.
, vol.23
, Issue.7
, pp. 561-568
-
-
Birkner, J.1
Chan, A.2
Chua, H.3
Chao, A.4
Gordon, K.5
Kleinman, B.6
Kolze, P.7
Wong, R.8
-
24
-
-
84990479742
-
An efficient heuristic procedure for partitioning graphs
-
Kernighan, B., Lin, S.: An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. 49, 291-307 (1970)
-
(1970)
Bell Syst. Tech. J.
, vol.49
, pp. 291-307
-
-
Kernighan, B.1
Lin, S.2
-
25
-
-
0015206785
-
On pin versus block relationship for partition of logic circuits
-
Landman, B., Russo, R.: On pin versus block relationship for partition of logic circuits. IEEE Trans. Comput. 20, 1469-1479 (1971)
-
(1971)
IEEE Trans. Comput.
, vol.20
, pp. 1469-1479
-
-
Landman, B.1
Russo, R.2
-
26
-
-
0025386807
-
Multilevel logic synthesis
-
Feb
-
Brayton, R., Hachtel, G., Sangiovanni-Vincentelli, A.: Multilevel logic synthesis. Proc. IEEE 78(2), 264-300 (Feb. 1990)
-
(1990)
Proc. IEEE
, vol.78
, Issue.2
, pp. 264-300
-
-
Brayton, R.1
Hachtel, G.2
Sangiovanni-Vincentelli, A.3
-
27
-
-
0002846615
-
The decomposition and factorization of Boolean expressions
-
Brayton, R., McMullen, C.: The decomposition and factorization of Boolean expressions. Proc. ISCAS, 29-54 (1982)
-
(1982)
Proc. ISCAS
, pp. 29-54
-
-
Brayton, R.1
McMullen, C.2
-
28
-
-
0034174174
-
The garp architecture and C compiler
-
April
-
Callahan, T. J., Hauser, J. R., Wawrzynek, J.: The garp architecture and C compiler. Computer 33(4), 62-69 (April 2000)
-
(2000)
Computer
, vol.33
, Issue.4
, pp. 62-69
-
-
Callahan, T.J.1
Hauser, J.R.2
Wawrzynek, J.3
-
29
-
-
0029701117
-
DP-FPGA: An FPGA architecture optimized for datapaths
-
Cherepacha, D., Lewis, D.: DP-FPGA: an FPGA architecture optimized for datapaths. VLSI Des. 4(4), 329-343 (1996)
-
(1996)
VLSI Des.
, vol.4
, Issue.4
, pp. 329-343
-
-
Cherepacha, D.1
Lewis, D.2
-
30
-
-
34547473719
-
Virtual embedded blocks: A methodology for evaluating embedded elements in FPGAs
-
Ho, C. H., Leong, P. H. W., Luk, W., Wilton, S., Lopez-Buedo, S.: Virtual embedded blocks: a methodology for evaluating embedded elements in FPGAs. In: FCMM, 35-44 (2006)
-
(2006)
FCMM
, pp. 35-44
-
-
Ho, C.H.1
Leong, P.H.W.2
Luk, W.3
Wilton, S.4
Lopez-Buedo, S.5
-
31
-
-
0030646148
-
Multilevel circuit partitioning
-
Alpert, C. J., Hagen, L. W., Kahng, A. B.: Multilevel circuit partitioning. In: Design Automation Conference, pp. 530-533 (1997)
-
(1997)
Design Automation Conference
, pp. 530-533
-
-
Alpert, C.J.1
Hagen, L.W.2
Kahng, A.B.3
-
32
-
-
0030717793
-
Faster minimization of linear wirelength for global placement
-
Alpert, C. J., Chan, T., Huang, D., Kahng, A., Markov, I., Mulet, P., Yan, K.: Faster minimization of linear wirelength for global placement. In: ACM Symposium on Physical Design, pp. 4-11 (1997)
-
(1997)
ACM Symposium on Physical Design
, pp. 4-11
-
-
Alpert, C.J.1
Chan, T.2
Huang, D.3
Kahng, A.4
Markov, I.5
Mulet, P.6
Yan, K.7
-
33
-
-
0022141776
-
Fat-trees: Universal networks for hardware efficient supercomputing
-
Oct
-
Leiserson C.: Fat-trees: universal networks for hardware efficient supercomputing. IEEE Trans. Comput. C34(10), 892-901 (Oct. 1985)
-
(1985)
IEEE Trans. Comput.
, vol.C34
, Issue.10
, pp. 892-901
-
-
Leiserson, C.1
-
35
-
-
34147186108
-
Automatic design of area-efficient configurable ASIC cores
-
May
-
Compton, K., Hauck, S.: Automatic design of area-efficient configurable ASIC cores. IEEE Trans. Comput. 56(5), 662-672 (May 2007)
-
(2007)
IEEE Trans. Comput.
, vol.56
, Issue.5
, pp. 662-672
-
-
Compton, K.1
Hauck, S.2
-
36
-
-
85032425236
-
-
Open core: http://www.opencores.org/(2009)
-
(2009)
-
-
Open core1
-
37
-
-
0021404023
-
The timberwolf placement and routing package
-
April
-
Sechen, C., Sangiovanni-Vincentelli, A.: The timberwolf placement and routing package. JSSC, 510-522 (April 1985)
-
(1985)
JSSC
, pp. 510-522
-
-
Sechen, C.1
Sangiovanni-Vincentelli, A.2
-
39
-
-
84969784748
-
When clusters meet partitions: New density based methods for circuit decomposition
-
Huang, D., Kahng, A.: When clusters meet partitions: new density based methods for circuit decomposition. In: IEEE European Design and Test Conference, pp. 60-64 (1995)
-
(1995)
IEEE European Design and Test Conference
, pp. 60-64
-
-
Huang, D.1
Kahng, A.2
-
40
-
-
0030646008
-
Partitioning-based standard-cell global placement with an exact objective
-
Huang, D., Kahng, A.: Partitioning-based standard-cell global placement with an exact objective. In: ACM Symposium on Physical Design, pp. 18-25 (1997)
-
(1997)
ACM Symposium on Physical Design
, pp. 18-25
-
-
Huang, D.1
Kahng, A.2
-
41
-
-
85032422019
-
-
eASIC: http://www.easic.com (2010)
-
(2010)
-
-
eASIC1
-
42
-
-
84955557263
-
RaPiD-Reconfigurable pipelined datapath
-
Ebeling, C., Cronquist, D. C., Franklin, P.: RaPiD-Reconfigurable pipelined datapath. In: Field Programmable Logic and Applications, pp. 126-135 (1996)
-
(1996)
Field Programmable Logic and Applications
, pp. 126-135
-
-
Ebeling, C.1
Cronquist, D.C.2
Franklin, P.3
-
43
-
-
2642513341
-
Routability-driven packing: Metrics and algorithms for clusterbased FPGAs
-
Bozorgzadeh, E., et al.: Routability-driven packing: metrics and algorithms for clusterbased FPGAs. IEEE J. Circuits Syst. Comput. 13(1), 77-100 (2004)
-
(2004)
IEEE J. Circuits Syst. Comput.
, vol.13
, Issue.1
, pp. 77-100
-
-
Bozorgzadeh, E.1
-
44
-
-
0024645788
-
An architecture for electrically configurable gate arrays
-
April
-
El Gamal, A., Greene, J., Reyneri, J., Rogoyski, E., El-Ayat, K., Mohsen, A.: An architecture for electrically configurable gate arrays. IEEE J. Solid-State Circuits 24(2), 394-398 (April 1989)
-
(1989)
IEEE J. Solid-state Circuits
, vol.24
, Issue.2
, pp. 394-398
-
-
El Gamal, A.1
Greene, J.2
Reyneri, J.3
Rogoyski, E.4
El-Ayat, K.5
Mohsen, A.6
-
45
-
-
70449504075
-
A new tree-based coarse-grained FPGA architecture
-
Ph. D
-
Farooq, U., Parvez, H., Marrakchi, Z., Mehrez, H.: A new tree-based coarse-grained FPGA architecture. Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph. D, pp. 48-51 (2009)
-
(2009)
Research in Microelectronics and Electronics, 2009. PRIME 2009
, pp. 48-51
-
-
Farooq, U.1
Parvez, H.2
Marrakchi, Z.3
Mehrez, H.4
-
46
-
-
62349141339
-
The effect of lut and cluster size on a tree based FGPA architecture
-
IEEE Computer Society, Washington, DC, USA
-
Farooq, U., Marrakchi, Z., Mrabet, H., Mehrez, H.: The effect of lut and cluster size on a tree based FGPA architecture. In: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs, pp. 115-120. IEEE Computer Society, Washington, DC, USA (2008). http://portal.acm.org/citation. cfm?id=1494647.1495190
-
(2008)
Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
, pp. 115-120
-
-
Farooq, U.1
Marrakchi, Z.2
Mrabet, H.3
Mehrez, H.4
-
47
-
-
85046457769
-
A linear-time heuristic for improving network partitions
-
Fiduccia, C. M., Mattheyeses, R. M.: A linear-time heuristic for improving network partitions. Proc. DAC, pp. 175-181 (1982)
-
(1982)
Proc. DAC
, pp. 175-181
-
-
Fiduccia, C.M.1
Mattheyeses, R.M.2
-
48
-
-
0030686036
-
Multilevel hypergraph partitioning: Applicationin VLSI design
-
Karypis, G., Aggarwal, R., Kumar, V., Shekhar, S.: Multilevel hypergraph partitioning: applicationin VLSI design. In: Design Automation Conference, pp. 526-529 (1997)
-
(1997)
Design Automation Conference
, pp. 526-529
-
-
Karypis, G.1
Aggarwal, R.2
Kumar, V.3
Shekhar, S.4
-
51
-
-
20344381220
-
Directional and single-driver wires in FPGA interconnect
-
Lemieux, G., Lee, E., Tom, M., Yu, A.: Directional and single-driver wires in FPGA interconnect. In: IEEE International Conference on Field-Programmable Technology (ICFPT), pp. 41-48 (2004)
-
(2004)
IEEE International Conference on Field-programmable Technology (ICFPT)
, pp. 41-48
-
-
Lemieux, G.1
Lee, E.2
Tom, M.3
Yu, A.4
-
52
-
-
12444323064
-
A high performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs
-
Govindu, G., Choi, S., Prasanna, V., Daga, V., Gangadharpalli, S., Sridhar, V.: A high performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs. In: Proceedings of the 18th International Parallel and Distributed Processing Symposium (2004)
-
(2004)
Proceedings of the 18th International Parallel and Distributed Processing Symposium
-
-
Govindu, G.1
Choi, S.2
Prasanna, V.3
Daga, V.4
Gangadharpalli, S.5
Sridhar, V.6
-
53
-
-
0026174925
-
Analytical placement: A linear or a quadratic objective function?
-
Sigl, G., Doll, K., Johannes, F.: Analytical placement: a linear or a quadratic objective function? In: Design Automation Conference, pp. 427-432 (1991)
-
(1991)
Design Automation Conference
, pp. 427-432
-
-
Sigl, G.1
Doll, K.2
Johannes, F.3
-
54
-
-
0018454998
-
An electrically alterable nonvolatile memory cell using a floating-gate structure
-
April
-
Guterman, D. C., Rimawi, I. H., Chiu, T. L., Halvorson, R., McElroy, D.: An electrically alterable nonvolatile memory cell using a floating-gate structure. IEEE Trans. Electron Devices 26(4), 576-586 (April 1979)
-
(1979)
IEEE Trans. Electron Devices
, vol.26
, Issue.4
, pp. 576-586
-
-
Guterman, D.C.1
Rimawi, I.H.2
Chiu, T.L.3
Halvorson, R.4
McElroy, D.5
-
55
-
-
0024169876
-
Dielectric based antifuse for logic and memory ICs
-
Technical Digest
-
Hamdy, E., McCollum, J., Chen, S., Chiang, S., Eltoukhy, S., Chang, J., Speers, T., Mohsen, A.:: Dielectric based antifuse for logic and memory ICs. In: IEEE International Electron Devices Meeting, IEDM'88, Technical Digest, pp. 786-789 (1988)
-
(1988)
IEEE International Electron Devices Meeting, IEDM'88
, pp. 786-789
-
-
Hamdy, E.1
McCollum, J.2
Chen, S.3
Chiang, S.4
Eltoukhy, S.5
Chang, J.6
Speers, T.7
Mohsen, A.8
-
56
-
-
85032418769
-
-
HardCopy: HardCopy IV ASICs, device handbook. Available at http://www.altera.com/products/devices/hardcopy-asics/hardcopy-iv/literature/hcivliterature.jsp (IV)
-
HardCopy IV ASICs, Device Handbook
-
-
HardCopy1
-
57
-
-
84938156739
-
An FPGA Implement
-
Hauck, S., Burns, S., Borriello, G., Ebeling, C.: An FPGA Implement. Asynchronous Circuits. IEEE Des. Test 11(3), 60-69 (1994)
-
(1994)
Asynchronous Circuits. IEEE Des. Test
, vol.11
, Issue.3
, pp. 60-69
-
-
Hauck, S.1
Burns, S.2
Borriello, G.3
Ebeling, C.4
-
58
-
-
34547473719
-
Virtual embedded blocks: A methodology for evaluating embedded elements in FPGAs
-
Ho, C., Leong, P., Luk, W., Wilton, S., Lopez-Buedo, S.: Virtual embedded blocks: a methodology for evaluating embedded elements in FPGAs. In: Proceedings of the FCCM, pp. 35-44 (2006)
-
(2006)
Proceedings of the FCCM
, pp. 35-44
-
-
Ho, C.1
Leong, P.2
Luk, W.3
Wilton, S.4
Lopez-Buedo, S.5
-
59
-
-
34047214748
-
A methodology for FPGA to structured-ASIC synthesis and verification
-
March
-
Hutton, M., Yuan, R., Schleicher, J., Baeckler, G., Cheung, S., Chua, K., Phoon, H.: A methodology for FPGA to structured-ASIC synthesis and verification. DATE 2, 64-69 (March 2006)
-
(2006)
DATE
, vol.2
, pp. 64-69
-
-
Hutton, M.1
Yuan, R.2
Schleicher, J.3
Baeckler, G.4
Cheung, S.5
Chua, K.6
Phoon, H.7
-
60
-
-
33846634193
-
Measuring the gap between FPGAs and ASICs
-
Kuon, I., Rose, J.: Measuring the gap between FPGAs and ASICs. IEEE Trans. CAD 26(2), 203-215 (2007)
-
(2007)
IEEE Trans. CAD
, vol.26
, Issue.2
, pp. 203-215
-
-
Kuon, I.1
Rose, J.2
-
61
-
-
0026944167
-
A very-high-speed field programmable gate array using metal-to-metal antifuse programmable elements
-
Nov
-
Birkner, J., Chan, A., Chua, H. T., Chao, A., Gordon, K., Kleinman, B., Kolze, P., Wong, R.:: A very-high-speed field programmable gate array using metal-to-metal antifuse programmable elements. Micro 23(7), 561-568 (Nov. 1992)
-
(1992)
Micro
, vol.23
, Issue.7
, pp. 561-568
-
-
Birkner, J.1
Chan, A.2
Chua, H.T.3
Chao, A.4
Gordon, K.5
Kleinman, B.6
Kolze, P.7
Wong, R.8
-
63
-
-
77949379091
-
-
Jamieson, P., Luk, W., Wilton, S., Constantinides, G.: An Energy and Power Consumption Analysis of FPGA Routing Architectures, pp. 324-327 (2009)
-
(2009)
An Energy and Power Consumption Analysis of FPGA Routing Architectures
, pp. 324-327
-
-
Jamieson, P.1
Luk, W.2
Wilton, S.3
Constantinides, G.4
-
64
-
-
0028259317
-
Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA Designs
-
Cong, J., Ding, Y.: Flowmap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA Designs. IEEE Trans. CAD, pp. 1-12 (1994)
-
(1994)
IEEE Trans. CAD
, pp. 1-12
-
-
Cong, J.1
Ding, Y.2
-
65
-
-
0028455029
-
On area/depth trade-off in LUT-based FPGA technology mapping
-
Cong, J., Ding, Y.: On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 2(2), 137-148 (1994)
-
(1994)
IEEE Trans. VLSI Syst.
, vol.2
, Issue.2
, pp. 137-148
-
-
Cong, J.1
Ding, Y.2
-
66
-
-
23044521062
-
Structural gate decomposition for depth-optimal technology in LUT-based FPGA designs
-
Cong, J., Ding, Y.: Structural gate decomposition for depth-optimal technology in LUT-based FPGA designs. ACM Trans. Des. Autom. Electron. Syst. 5 (3) (2000)
-
(2000)
ACM Trans. Des. Autom. Electron. Syst.
, vol.5
, Issue.3
-
-
Cong, J.1
Ding, Y.2
-
68
-
-
0026962312
-
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
-
Frankle, J.: Iterative and adaptive slack allocation for performance-driven layout and FPGA routing. In: ACM/IEEE Design Automation Conference, pp. 536-542 (1992)
-
(1992)
ACM/IEEE Design Automation Conference
, pp. 536-542
-
-
Frankle, J.1
-
70
-
-
20344380201
-
An FPGA-based VLIW processor with custom hardware execution
-
Jones, A. K., Hoare, R., Kusic, D., Fazekas, J., Foster, J.: An FPGA-based VLIW processor with custom hardware execution. In: Proceedings of the International Symposium on Field Programmable Gate Arrays, pp. 107-117 (2005)
-
(2005)
Proceedings of the International Symposium on Field Programmable Gate Arrays
, pp. 107-117
-
-
Jones, A.K.1
Hoare, R.2
Kusic, D.3
Fazekas, J.4
Foster, J.5
-
71
-
-
0025505369
-
Architecture of field-programmable gate arrays: The effect of logic functionality on area efficiency
-
Oct
-
Rose, J., Francis, R., Lewis, D., Chow, P.: Architecture of field-programmable gate arrays: the effect of logic functionality on area efficiency. IEEE J. Solid State Circuits 25(5), 1217-1225 (Oct. 1990)
-
(1990)
IEEE J. Solid State Circuits
, vol.25
, Issue.5
, pp. 1217-1225
-
-
Rose, J.1
Francis, R.2
Lewis, D.3
Chow, P.4
-
72
-
-
33745805907
-
Measuring the gap between FPGAs and ASICs
-
ACM New York, NY
-
Kuon, I., Rose, J.: Measuring the gap between FPGAs and ASICs. In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, pp. 21-30, ACM New York, NY (2006)
-
(2006)
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays
, pp. 21-30
-
-
Kuon, I.1
Rose, J.2
-
74
-
-
0015206785
-
On pin versus block relationship for partition of logic circuits
-
Landman, B., Russo, R.: On pin versus block relationship for partition of logic circuits. IEEE Trans. Comput. 20, 1469-1479 (1971)
-
(1971)
IEEE Trans. Comput.
, vol.20
, pp. 1469-1479
-
-
Landman, B.1
Russo, R.2
-
75
-
-
0024481167
-
Multiple-way network partitioning
-
Sanchis, L. A.: Multiple-way network partitioning. IEEE Trans. Comput. 38(1), 62-81 (1989)
-
(1989)
IEEE Trans. Comput.
, vol.38
, Issue.1
, pp. 62-81
-
-
Sanchis, L.A.1
-
77
-
-
20344381220
-
Directional and single-driver wires in FPGA interconnect
-
Lemieux, G., Lee, E., Tom, M., Yu, A.: Directional and single-driver wires in FPGA interconnect. In: IEEE International Conference on Field-Programmable Technology (ICFPT), pp. 41-48 (2004)
-
(2004)
IEEE International Conference on Field-programmable Technology (ICFPT)
, pp. 41-48
-
-
Lemieux, G.1
Lee, E.2
Tom, M.3
Yu, A.4
-
78
-
-
0031176484
-
Combining problem reduction and adaptive multi-start: A new technique for superior iterative partitioning
-
Hagen, L., Kahng, A.: Combining problem reduction and adaptive multi-start: a new technique for superior iterative partitioning. In: IEEE Trans. CAD, pp. 92-98 (1997)
-
(1997)
IEEE Trans. CAD
, pp. 92-98
-
-
Hagen, L.1
Kahng, A.2
-
79
-
-
85032418846
-
-
Lip6: http://www-asim.lip6.fr (2007)
-
(2007)
-
-
Lip61
-
81
-
-
67650659766
-
VPR 5.0: FPGACAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
-
Feb
-
Luu, J., Kuon, I., Jamieson, P., Campbell, T., Ye, A., Fang, W. M., Rose, J.: VPR 5.0: FPGACAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. In: FPGA, pp. 133-142 (Feb. 2009)
-
(2009)
FPGA
, pp. 133-142
-
-
Luu, J.1
Kuon, I.2
Jamieson, P.3
Campbell, T.4
Ye, A.5
Fang, W.M.6
Rose, J.7
-
83
-
-
0032672691
-
A reconfigurable arithmetic array for multimedia applications
-
Marshall, A., Stansfield, T., Kostarnov, I., Vuillemin, J., Hutchings, B.: A reconfigurable arithmetic array for multimedia applications. In: International Symposium on Field Programmable Gate Arrays, pp. 135-143 (1999)
-
(1999)
International Symposium on Field Programmable Gate Arrays
, pp. 135-143
-
-
Marshall, A.1
Stansfield, T.2
Kostarnov, I.3
Vuillemin, J.4
Hutchings, B.5
-
86
-
-
0022982761
-
An efficient general cooling schedule for simulated annealing
-
Huang, M., Romeo, F., Sangiovanni-Vincentelli, A.: An efficient general cooling schedule for simulated annealing. In: ICCAD, pp. 381-384 (1986)
-
(1986)
ICCAD
, pp. 381-384
-
-
Huang, M.1
Romeo, F.2
Sangiovanni-Vincentelli, A.3
-
87
-
-
0035022183
-
Timing-driven placement for hierarchical programmable logic devices
-
Hutton, M., Adibsamii, K., Leaver, A.: Timing-driven placement for hierarchical programmable logic devices. In: International Symposium on Field Programmable Gate Array, pp. 3-11 (2001)
-
(2001)
International Symposium on Field Programmable Gate Array
, pp. 3-11
-
-
Hutton, M.1
Adibsamii, K.2
Leaver, A.3
-
89
-
-
63049083687
-
Delay evaluation of 90 nm CMOS multi-context FPGA with shiftregistertype temporal communication module for large-scale circuit emulation
-
Miyamoto, N., Ohmi, T.: Delay evaluation of 90 nm CMOS multi-context FPGA with shiftregistertype temporal communication module for large-scale circuit emulation. In: IEEE International Conference on Field Programmable Technology (ICFPT), pp. 365-368 (2008)
-
(2008)
IEEE International Conference on Field Programmable Technology (ICFPT)
, pp. 365-368
-
-
Miyamoto, N.1
Ohmi, T.2
-
90
-
-
84870650637
-
-
NIOS: NIOS II processor. Available at http://www.altera.com/products/ip/processors/nios2/ni2-index.html (II)
-
NIOS II Processor
-
-
NIOS1
-
91
-
-
2942654761
-
Design methodology and tools for NEC electronics structured ASIC
-
April
-
Okamoto, T., Kimoto, T., Maeda, N.: Design methodology and tools for NEC electronics structured ASIC. In: Proceedings of the ISPD, pp. 90-96 (April 2004)
-
(2004)
Proceedings of the ISPD
, pp. 90-96
-
-
Okamoto, T.1
Kimoto, T.2
Maeda, N.3
-
92
-
-
63049135025
-
A new coarse-grained FPGA architecture exploration environment
-
Parvez, H., Marrakchi, Z., Farooq, U., Mehrez, H.: A new coarse-grained FPGA architecture exploration environment. In: IEEE International Conference on ICECE Technology. FPT 2008, pp. 285-288 (2008)
-
(2008)
IEEE International Conference on ICECE Technology. FPT 2008
, pp. 285-288
-
-
Parvez, H.1
Marrakchi, Z.2
Farooq, U.3
Mehrez, H.4
-
93
-
-
77949392470
-
ASIF: Application specific inflexible FPGA
-
Parvez, H., Marrakchi, Z., Mehrez, H.: ASIF: Application specific inflexible FPGA. In: International Conference on Field-Programmable Technology (FPT), pp. 112-119 (2009)
-
(2009)
International Conference on Field-programmable Technology (FPT)
, pp. 112-119
-
-
Parvez, H.1
Marrakchi, Z.2
Mehrez, H.3
-
95
-
-
12744272158
-
A fast hierarchical approach to FPGA placement
-
Du, P., Grewal, G. W., Areibi, S., Banerji, D. K.: A Fast Hierarchical Approach to FPGA Placement. In: ESA/VLSI, pp. 497-503 (2004)
-
(2004)
ESA/VLSI
, pp. 497-503
-
-
Du, P.1
Grewal, G.W.2
Areibi, S.3
Banerji, D.K.4
-
97
-
-
84893687806
-
Ageneric architecture for on chip packet-switched interconnections
-
Paris, France, Mar
-
Guerrier, P., Greiner, A.: Ageneric architecture for on chip packet-switched interconnections. In: Proceedings of the Design Automation and Test in Europe Conference 2000 (DATE 2000), Paris, France pp. 250-256 (Mar. 2000)
-
(2000)
Proceedings of the Design Automation and Test in Europe Conference 2000 (DATE 2000)
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
98
-
-
48149110140
-
Equivalence verification of FPGA and structured ASIC implementations
-
Aug
-
Pistorius, J., Hutton, M., Schleicher, J., Iotov, M., Julias, E., Tharmalignam, K.: Equivalence verification of FPGA and structured ASIC implementations. In: FPL'07, pp. 423-428 (Aug. 2007)
-
(2007)
FPL'07
, pp. 423-428
-
-
Pistorius, J.1
Hutton, M.2
Schleicher, J.3
Iotov, M.4
Julias, E.5
Tharmalignam, K.6
-
100
-
-
0027042493
-
On clustering for minimum delay/area
-
Murgai, R., Brayton, R., Sangiovanni-Vincentelli, A.: On clustering for minimum delay/area. In: IEEE International Conference on Computer Aided Design, pp. 6-9 (1991)
-
(1991)
IEEE International Conference on Computer Aided Design
, pp. 6-9
-
-
Murgai, R.1
Brayton, R.2
Sangiovanni-Vincentelli, A.3
-
103
-
-
2942659249
-
Design considerations for regular fabrics
-
April
-
Sherlekar, D.: Design considerations for regular fabrics. In: Procedings of the ISPD, pp. 97-102 (April 2004)
-
(2004)
Procedings of the ISPD
, pp. 97-102
-
-
Sherlekar, D.1
-
104
-
-
84885756209
-
An 8x8 IDCT implementation on an FPGA-augmented trimedia
-
Sima, M., Cotofana, S., Van Eijndhoven, J. T. J., Vassiliadis, S., Vissers, K.: An 8x8 IDCT implementation on an FPGA-augmented trimedia. In: Proceedings of the 9th Annual IEEE Symposium on Field Programmable Custom Computing Machines, pp. 160-169 (2001)
-
(2001)
Proceedings of the 9th Annual IEEE Symposium on Field Programmable Custom Computing Machines
, pp. 160-169
-
-
Sima, M.1
Cotofana, S.2
Van Eijndhoven, J.T.J.3
Vassiliadis, S.4
Vissers, K.5
-
105
-
-
26444479778
-
Optimization by simulated annealing
-
Kirkpatrick, S., Gelatt, C. D., Vecchi, M. P.: Optimization by simulated annealing. Science 220, 671-680 (1983)
-
(1983)
Science
, vol.220
, pp. 671-680
-
-
Kirkpatrick, S.1
Gelatt, C.D.2
Vecchi, M.P.3
-
106
-
-
85032395914
-
-
Stratix: Stratix II FPGAs. Available at http://www.altera.com/products/devices/stratix2/st2-index.jsp (II)
-
Stratix II FPGAs
-
-
Stratix1
-
107
-
-
85032399322
-
-
Stratix: Stratix IV FPGAs, device handbook. Available at http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/literature/stiv-literature.jsp (IV)
-
Stratix IV FPGAs, Device Handbook
-
-
Stratix1
-
109
-
-
85032412798
-
-
Tabula: http://www.tabula.com (2010)
-
(2010)
-
-
Tabula1
-
110
-
-
51249170866
-
Graph bisection algorithms with good average behavior
-
Bui, T., Chaudhuri, S., Leighton, T., Sipser, M.: Graph Bisection Algorithms with Good Average Behavior. Combinatorica (1987)
-
(1987)
Combinatorica
-
-
Bui, T.1
Chaudhuri, S.2
Leighton, T.3
Sipser, M.4
-
111
-
-
0004116989
-
-
MIT Press, Cambridge
-
Cormen, T., Leiserson, C., Rivest, R.: Introduction to Algorithms. MIT Press, Cambridge (1990)
-
(1990)
Introduction to Algorithms
-
-
Cormen, T.1
Leiserson, C.2
Rivest, R.3
-
112
-
-
8744285527
-
An asynchronous dataflow FPGA architecture
-
Teifel, J., Manohar, R.: An asynchronous dataflow FPGA architecture. IEEE Trans. Comput. 53(11), 1376-1392 (2004)
-
(2004)
IEEE Trans. Comput.
, vol.53
, Issue.11
, pp. 1376-1392
-
-
Teifel, J.1
Manohar, R.2
-
113
-
-
85032412664
-
-
Tierlogic: http://www.tierlogic.com (2010)
-
(2010)
-
-
Tierlogic1
-
114
-
-
0031346317
-
-
Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A Time-Multiplexed FPGA. pp. 22-28 (1997)
-
(1997)
A Time-multiplexed FPGA.
, pp. 22-28
-
-
Trimberger, S.1
Carberry, D.2
Johnson, A.3
Wong, J.4
-
115
-
-
85032412685
-
Comparison between heterogeneous meshbased and tree-based application specific FPGA
-
Farooq, U., Husain Parvez, Z. M., Mehrez, H.: Comparison between heterogeneous meshbased and tree-based application specific FPGA. In: 7th International Symposium on Applied Reconfigurable Computing (ARC'11), pp. 218-219 (2011)
-
(2011)
7th International Symposium on Applied Reconfigurable Computing (ARC'11)
, pp. 218-219
-
-
Farooq, U.1
Husain Parvez, Z.M.2
Mehrez, H.3
-
119
-
-
85032422091
-
-
Toronto University: http://www.eecg.utoronto.ca/vpr/(2009)
-
(2009)
-
-
Toronto University1
-
120
-
-
84957870821
-
VPR: A new packing placement and routing tool for FPGA Research
-
Betz, V., Rose, J.: VPR: a new packing placement and routing tool for FPGA Research. In: International Workshop on FPGA, pp. 213-222 (1997)
-
(1997)
International Workshop on FPGA
, pp. 213-222
-
-
Betz, V.1
Rose, J.2
-
121
-
-
0022599035
-
A user programmable reconfiguration gate array
-
May
-
Carter, W., Duong, K., Freeman, R., Sze, S.: A user programmable reconfiguration gate array. In: IEEE Custom Integrated Circuits Conference, pp. 233-235 (May 1986)
-
(1986)
IEEE Custom Integrated Circuits Conference
, pp. 233-235
-
-
Carter, W.1
Duong, K.2
Freeman, R.3
Sze, S.4
-
122
-
-
0022599035
-
A user programmable reconfiguration gate array
-
May
-
Carter, W., Duong, K., Freeman, R. H., Hsieh, H., Ja, Y. J, Mahoney, J. E., Ngo, L T., Sze, S. L.:: A user programmable reconfiguration gate array. In: IEEE Custom Integrated Circuits Conference, pp. 233-235 (May 1986)
-
(1986)
IEEE Custom Integrated Circuits Conference
, pp. 233-235
-
-
Carter, W.1
Duong, K.2
Freeman, R.H.3
Hsieh, H.4
Ja, Y.J.5
Mahoney, J.E.6
Ngo, L.T.7
Sze, S.L.8
-
124
-
-
0024665580
-
A 5000-gate CMOS EPLD with multiple logic and interconnect arrays
-
Wong, S., So, H., Ou, J., Costello, J.: A 5000-gate CMOS EPLD with multiple logic and interconnect arrays. In: Proceedings of the IEEE Custom Integrated Circuits Conference (1989), pp. 5-8 (2002)
-
(1989)
Proceedings of the IEEE Custom Integrated Circuits Conference
, pp. 5-8
-
-
Wong, S.1
So, H.2
Ou, J.3
Costello, J.4
-
125
-
-
2942644083
-
Structured ASIC, evolution or revolution
-
April
-
Wu, K., Tsai, Y.: Structured ASIC, evolution or revolution. In: Proceedings of the ISPD, pp. 103-106 (April 2004)
-
(2004)
Proceedings of the ISPD
, pp. 103-106
-
-
Wu, K.1
Tsai, Y.2
-
126
-
-
85032416267
-
-
Xilinx: Xilinx. http://www.xilinx.com (2010)
-
(2010)
Xilinx
-
-
Xilinx1
-
127
-
-
0242443754
-
-
Ye, A., Rose, J., Lewis, D.: Architecture of datapath-oriented coarse-grain logic and routing for FPGAs, pp. 61-66 (2003)
-
(2003)
Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs
, pp. 61-66
-
-
Ye, A.1
Rose, J.2
Lewis, D.3
-
128
-
-
33746461451
-
Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits
-
May
-
Ye, A. G., Rose, J.: Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(5), 462-473 (May 2006)
-
(2006)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.14
, Issue.5
, pp. 462-473
-
-
Ye, A.G.1
Rose, J.2
-
129
-
-
0031169872
-
Hierarchical interconnection structures for field programmable gate arrays
-
Lay, Y., Wang, P.: Hierarchical interconnection structures for field programmable gate arrays. IEEE Trans. VLSI Syst. 5(2), 186-196 (1997)
-
(1997)
IEEE Trans. VLSI Syst.
, vol.5
, Issue.2
, pp. 186-196
-
-
Lay, Y.1
Wang, P.2
-
130
-
-
85032416264
-
Trading quality for compile time: Ultra-fast placement for FPGAs
-
Sanker, Y., Rose, J.: Trading quality for compile time: ultra-fast placement for FPGAs. In: International FPGA symposium (1999)
-
(1999)
International FPGA Symposium
-
-
Sanker, Y.1
Rose, J.2
-
132
-
-
79951715282
-
FPGA interconnect topologies exploration
-
Zied, M., Hayder, M., Umer, F., Habib, M.: FPGA interconnect topologies exploration. Internat. J. Reconfigurable Comput. (2009)
-
(2009)
Internat. J. Reconfigurable Comput.
-
-
Zied, M.1
Hayder, M.2
Umer, F.3
Habib, M.4
-
133
-
-
33750325749
-
Hierarchical FPGA clustering to improve routability
-
Marrakchi, Z., Mrabet, H., Mehrez, H.: Hierarchical FPGA clustering to improve routability. In: Conference on Ph. D Research in Microelectronics and Electronics, PRIME (2005)
-
(2005)
Conference on Ph. D Research in Microelectronics and Electronics, PRIME
-
-
Marrakchi, Z.1
Mrabet, H.2
Mehrez, H.3
|