Structural gate decomposition for depthoptimal technology mapping in LUTBased FPGA designs

ACM Transactions on Design Automation of Electronic Systems

Volumn 5, Issue 2, 2000, Pages 193-225

  Cong, Jason ^a,b   Hwang, Yean Yow ^a,b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Engineering IV   (United States)

Author keywords

Computer aided design of vlsi; Decomposition; Delay minimization; Fpga, logic optimization; Programmable logic; Simplification; Synthesis; System design; Technology mapping

Indexed keywords

EID: 23044521062     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/335043.335045     Document Type: Article

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