-
6
-
-
84858914236
-
-
Cadence Design Systems. TSMC Standard Cell Libraries, 2003. Available online at http://www.cadence.com/partners/tsmc/SC_Brochure_9.pdf.
-
(2003)
TSMC Standard Cell Libraries
-
-
-
7
-
-
27944486552
-
Explaining the gap between ASIC and custom power: A custom perspective
-
New York, NY, USA. ACM Press
-
A. Chang and W. J. Dally. Explaining the gap between ASIC and custom power: a custom perspective. In DAC '05, pages 281-284, New York, NY, USA, 2005. ACM Press.
-
(2005)
DAC '05
, pp. 281-284
-
-
Chang, A.1
Dally, W.J.2
-
9
-
-
27944462668
-
Closing the power gap between ASIC and custom: An ASIC perspective
-
New York, NY, USA. ACM Press
-
D. G. Chinnery and K. Keutzer. Closing the power gap between ASIC and custom: an ASIC perspective. In DAC '05, pages 275-280, New York, NY, USA, 2005. ACM Press.
-
(2005)
DAC '05
, pp. 275-280
-
-
Chinnery, D.G.1
Keutzer, K.2
-
10
-
-
33745840737
-
-
Altera Corporation. Private Communication
-
R. Cliff. Altera Corporation. Private Communication.
-
-
-
Cliff, R.1
-
11
-
-
34147186108
-
Automatic design of area-efficient configurable ASIC cores
-
submitted
-
K. Compton and S. Hauck. Automatic design of area-efficient configurable ASIC cores. IEEE Transactions on Computers, submitted.
-
IEEE Transactions on Computers
-
-
Compton, K.1
Hauck, S.2
-
12
-
-
0033682589
-
The role of custom design in ASIC chips
-
W. J. Dally and A. Chang. The role of custom design in ASIC chips. In DAC '00, pages 643-647, 2000.
-
(2000)
DAC '00
, pp. 643-647
-
-
Dally, W.J.1
Chang, A.2
-
13
-
-
0033362679
-
Technology and design challenges for low power and high performance
-
New York, NY, USA. ACM Press
-
V. De and S. Borkar. Technology and design challenges for low power and high performance. In ISLPED '99, pages 163-168, New York, NY, USA, 1999. ACM Press.
-
(1999)
ISLPED '99
, pp. 163-168
-
-
De, V.1
Borkar, S.2
-
14
-
-
84962324887
-
Topological analysis for leakage prediction of digital circuits
-
Washington, DC, USA. IEEE Computer Society
-
W. Jiang, V. Tiwari, E. de la Iglesia, and A. Sinha. Topological analysis for leakage prediction of digital circuits. In ASP-DAC '02, page 39, Washington, DC, USA, 2002. IEEE Computer Society.
-
(2002)
ASP-DAC '02
, pp. 39
-
-
Jiang, W.1
Tiwari, V.2
De La Iglesia, E.3
Sinha, A.4
-
15
-
-
0022583256
-
A comparison of standard cell and gate array implementations in a common CAD system
-
H. S. Jones Jr., P. R. Nagle, and H. T. Nguyen. A comparison of standard cell and gate array implementations in a common CAD system. In IEEE 1986 CICC, pages 228-232, 1986.
-
(1986)
IEEE 1986 CICC
, pp. 228-232
-
-
Jones Jr., H.S.1
Nagle, P.R.2
Nguyen, H.T.3
-
16
-
-
20344391427
-
Design, layout and verification of an FPGA using automated tools
-
New York, NY, USA. ACM Press
-
I. Kuon, A. Egier, and J. Rose. Design, layout and verification of an FPGA using automated tools. In FPGA '05, pages 215-226, New York, NY, USA, 2005. ACM Press.
-
(2005)
FPGA '05
, pp. 215-226
-
-
Kuon, I.1
Egier, A.2
Rose, J.3
-
17
-
-
34548771503
-
-
May. Version 01.6
-
Lattice Semiconductor Corporation. LatticeECP/EC Family Data Sheet, May 2005. Version 01.6.
-
(2005)
LatticeECP/EC Family Data Sheet
-
-
-
18
-
-
84858929074
-
-
LSI Logic. RapidChip Platform ASIC, 2005. http://www.lsilogic.com/products/rapidchip_platform.asic/index.html.
-
(2005)
RapidChip Platform ASIC
-
-
-
19
-
-
84858927817
-
-
NEC Electronics. ISSP (Structured ASIC), 2005. http://www.necel.com/issp/english/.
-
(2005)
ISSP (Structured ASIC)
-
-
-
20
-
-
0038005995
-
Automatic transistor and physical design of FPGA tiles from an architectural specification
-
New York, NY, USA. ACM Press
-
K. Padalia, R. Fung, M. Bourgeault, A. Egier, and J. Rose. Automatic transistor and physical design of FPGA tiles from an architectural specification. In FPGA '03, pages 164-172, New York, NY, USA, 2003. ACM Press.
-
(2003)
FPGA '03
, pp. 164-172
-
-
Padalia, K.1
Fung, R.2
Bourgeault, M.3
Egier, A.4
Rose, J.5
-
22
-
-
33745846083
-
-
STMicroelectronics. 90nm CMOS090 Design Platform, 2005. http://www.st.com/stonline/prodpres/dedicate/soc/asic/90plat.htm.
-
(2005)
90Nm CMOS090 Design Platform
-
-
-
25
-
-
84858913490
-
-
BCE0012A
-
Toshiba Corporation. 90nm (Ldrawn=70nm) CMOS ASIC TC300 Family, BCE0012A, 2003. Available online at http://www.semicon.toshiba.co.jp/eng/prd/asic/doc/pdf/bce0012a.pdf.
-
(2003)
90Nm (Ldrawn=70nm) CMOS ASIC TC300 Family
-
-
-
27
-
-
13444309473
-
Design considerations for soft embedded programmable logic cores
-
February
-
S. J. Wilton, N. Kafafi, J. C. H. Wu, K. A. Bozman, V. Aken'Ova, and R. Saleh. Design considerations for soft embedded programmable logic cores. IEEE JSSC, 40(2):485-497, February 2005.
-
(2005)
IEEE JSSC
, vol.40
, Issue.2
, pp. 485-497
-
-
Wilton, S.J.1
Kafafi, N.2
Wu, J.C.H.3
Bozman, K.A.4
Aken'Ova, V.5
Saleh, R.6
-
29
-
-
0037387687
-
Routability-driven white space allocation for fixed-die standard-cell placement
-
April
-
X. Yang, B.-K. Choi, and M. Sarrafzadeh. Routability-driven white space allocation for fixed-die standard-cell placement. IEEE Trans. Computer-Aided Design, 22(4):410-419, April 2003.
-
(2003)
IEEE Trans. Computer-aided Design
, vol.22
, Issue.4
, pp. 410-419
-
-
Yang, X.1
Choi, B.-K.2
Sarrafzadeh, M.3
-
30
-
-
0036907308
-
A hybrid ASIC and FPGA architecture
-
November
-
P. S. Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and B. Troxel. A hybrid ASIC and FPGA architecture. In ICCAD '02, pages 187-194, November 2002.
-
(2002)
ICCAD '02
, pp. 187-194
-
-
Zuchowski, P.S.1
Reynolds, C.B.2
Grupp, R.J.3
Davis, S.G.4
Cremen, B.5
Troxel, B.6
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