Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 5, 2006, Pages 462-473

  Ye, Andy ^a,b   Rose, Jonathan ^a,c  

^a IEEE   (Canada)

^b RYERSON UNIVERSITY   (Canada)

^c UNIVERSITY OF TORONTO   (Canada)

Author keywords

Area efficiency; Datapath regularity; Field programmable gate arrays (FPGAs); Reconfigurable fabric; Routing architecture

Indexed keywords

AREA EFFICIENCY; DATAPATH REGULARITY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE FABRICS; ROUTING ARCHITECTURE;

COMPUTER ARCHITECTURE; DATA PROCESSING; ELECTRIC CONNECTORS; NETWORKS (CIRCUITS); PARALLEL PROCESSING SYSTEMS; ROUTERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746461451     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.876095     Document Type: Article

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