Virtual embedded blocks: A methodology for evaluating embedded elements in FPGAs

Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006

Volumn , Issue , 2006, Pages 35-44

  Ho, C H ^a   Leong, P H W ^a   Luk, W ^a   Wilton, S J E ^b   Lopez Buedo, S ^c  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^c UNIVERSIDAD AUTÓNOMA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMAL MAPPING; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MULTIPLYING CIRCUITS; ROUTING ALGORITHMS; TIMING CIRCUITS; VIRTUAL REALITY;

EMBEDDED ELEMENTS; TIMING ANALYSIS TOOLS; VIRTUAL EMBEDDED BLOCKS (VEB);

EMBEDDED SYSTEMS;

EID: 34547473719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.71     Document Type: Conference Paper

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