VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 133-142

  Luu, Jason ^a   Kuon, Ian ^a   Jamieson, Peter ^a   Campbell, Ted ^a   Ye, Andy ^a   Fang, Wei Mark ^a   Rose, Jonathan ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Architecture; CAD; FPGA

Indexed keywords

ARCHITECTURAL FEATURES; ARCHITECTURE EXPLORATION; CAD; CAPACITANCE PARAMETER; DIFFERENT PROCESS; ELECTRICAL DESIGN; ELECTRICAL MODELS; ELECTRICAL PROPERTY; FPGA; FPGA ARCHITECTURES; LOGIC BLOCKS; LUT SIZE; PROCESS SCALING; PROCESS TECHNOLOGIES; QUALITY OF RESULTS; REGRESSION TESTS; ROUTING ARCHITECTURE; TOOLSET;

AUTOMOBILE DRIVERS; COMPUTER AIDED DESIGN; ELECTRIC PROPERTIES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES;

ARCHITECTURE;

EID: 67650659766     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508150     Document Type: Conference Paper

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