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Volumn , Issue , 2003, Pages 61-64

Architecture of datapath-oriented coarse-grain logic and routing for FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; JAVA PROGRAMMING LANGUAGE; LOGIC DESIGN; STATIC RANDOM ACCESS STORAGE; TABLE LOOKUP;

EID: 0242443754     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (23)

References (18)
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    • Pico-Java Processor Design Documentation, Sun Microsystems Inc.
    • Pico-Java Processor Design Documentation, Sun Microsystems Inc., 1999.
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  • 3
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    • Xilinx Datasheet, Xilinx
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    • (2002)
  • 4
    • 0003793410 scopus 로고    scopus 로고
    • Architecture and CAD for deep-submicron FPGAs
    • Kluwer Academic Publishers
    • V. Betz, J. Rose, A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999.
    • (1999)
    • Betz, V.1    Rose, J.2    Marquardt, A.3
  • 5
    • 0004001585 scopus 로고
    • Field-programmable gate arrays
    • Kluwer Academic Publishers
    • S. Brown, R. Francis, J. Rose, Z. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.
    • (1992)
    • Brown, S.1    Francis, R.2    Rose, J.3    Vranesic, Z.4
  • 8
    • 0030211562 scopus 로고    scopus 로고
    • Performance optimization using template mapping for datapath-intensive high-level synthesis
    • August
    • M. R. Corazao, M. A. Khalaf, M. Potkonjak, J. M. Rabaey, "Performance optimization using template mapping for datapath-intensive high-level synthesis", Trans. on CAD, pp. 877-888, August 1996.
    • (1996) Trans. on CAD , pp. 877-888
    • Corazao, M.R.1    Khalaf, M.A.2    Potkonjak, M.3    Rabaey, J.M.4
  • 9
    • 0029713021 scopus 로고    scopus 로고
    • Structured design implementation - A strategy for implementing regular datapaths on FPGAs
    • A. Koch, "Structured design implementation - a strategy for implementing regular datapaths on FPGAs", Proc. of the ACM Fourth Int. Symp. on FPGA, pp. 151-157, 1996.
    • (1996) Proc. of the ACM Fourth Int. Symp. on FPGA , pp. 151-157
    • Koch, A.1
  • 10
    • 0029695758 scopus 로고    scopus 로고
    • Module compaction in FPGA-based regular datapaths
    • A. Koch, "Module compaction in FPGA-based regular datapaths", Proc. of the 33rd DAC, pp. 471-476, 1996.
    • (1996) Proc. of the 33rd DAC , pp. 471-476
    • Koch, A.1
  • 12
    • 0033680672 scopus 로고    scopus 로고
    • Efficient logic optimization using regularity extraction
    • T. Kutzschebauch, "Efficient logic optimization using regularity extraction", Proc. of Int. Conf. on Computer Design, pp. 487-493, 2000.
    • (2000) Proc. of Int. Conf. on Computer Design , pp. 487-493
    • Kutzschebauch, T.1
  • 16
    • 0032119196 scopus 로고    scopus 로고
    • Direct mapping of RTL structures onto LUT-based FPGAs
    • July
    • A. R. Naseer, M. Balakrishnan, A. Kumar, "Direct mapping of RTL structures onto LUT-based FPGAs", Trans. on CAD, pp. 624-631, July 1998.
    • (1998) Trans. on CAD , pp. 624-631
    • Naseer, A.R.1    Balakrishnan, M.2    Kumar, A.3
  • 17
    • 0242509404 scopus 로고    scopus 로고
    • FPGA architecture for datapath circuits
    • Ph.D. thesis is progress, University of Toronto
    • A. Ye, "FPGA architecture for datapath circuits", Ph.D. thesis is progress, University of Toronto, 2003.
    • (2003)
    • Ye, A.1
  • 18
    • 84962905473 scopus 로고    scopus 로고
    • Synthesizing datapath circuits for FPGAs with emphasis on area minimization
    • December
    • A. Ye, J. Rose, D. Lewis, "Synthesizing datapath circuits for FPGAs with emphasis on area minimization", IEEE Int. Conf. on Field-Programmable Technology, pp. 219-227, December 2002.
    • (2002) IEEE Int. Conf. on Field-Programmable Technology , pp. 219-227
    • Ye, A.1    Rose, J.2    Lewis, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.