An asynchronous dataflow FPGA architecture

IEEE Transactions on Computers

Volumn 53, Issue 11, 2004, Pages 1376-1392

  Teifel, John ^a   Manohar, Rajit ^a  

^a Cornell University ^*  (United States)

Author keywords

Asynchronous synchronous operation; Dataflow architectures; Gate arrays; Reconfigurable hardware

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; DATA FLOW ANALYSIS; LOGIC DEVICES; OPTIMIZATION;

ASYNCHRONOUS OPERATION; DATAFLOW ARCHITECTURE; LOGIC BLOCK; PIPELINED ASYNCHRONOUS CIRCUITS; PROGRAMMABLE ASYNCHRONOUS PIPELINES; RECONFIGURABLE HARDWARE; SYNCHRONOUS OPERATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 8744285527     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.88     Document Type: Article

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