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Volumn 26, Issue 2, 2007, Pages 266-277

Exploration and customization of FPGA-based soft processors

Author keywords

Customization; Design space exploration; Fleld programmable gate array (FPGA) based soft core processors; Processor generator

Indexed keywords

CUSTOMIZATION TECHNIQUE; DESIGN SPACE EXPLORATION; PROCESSOR GENERATORS; SOFT PROCESSORS;

EID: 33846640572     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.887921     Document Type: Conference Paper
Times cited : (53)

References (30)
  • 1
    • 33846603550 scopus 로고    scopus 로고
    • Online, Available
    • Nias II, Altera. [Online]. Available: http://www.altera.com/ products/ip/processors/nios2
    • Altera
    • II, N.1
  • 2
    • 67649541770 scopus 로고    scopus 로고
    • Online, Available
    • MicroBlaze, Xilinx. [Online], Available: http://www.xilinx.com/ microblaze
    • Xilinx
    • MicroBlaze1
  • 3
    • 33745869295 scopus 로고    scopus 로고
    • Survey: Who uses custom chips
    • Aug
    • J. Turley, "Survey: Who uses custom chips," Embedded Systems Programming, vol. 18, no. 8, Aug. 2005.
    • (2005) Embedded Systems Programming , vol.18 , Issue.8
    • Turley, J.1
  • 4
    • 33745805907 scopus 로고    scopus 로고
    • Measuring the gap between FPGAs and ASICs
    • I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," in Proc. FPGA, 2006, pp. 21-30.
    • (2006) Proc. FPGA , pp. 21-30
    • Kuon, I.1    Rose, J.2
  • 6
    • 33745813573 scopus 로고    scopus 로고
    • Application-specific customization of soft processor microarchitecture
    • P. Yiannacouras, J. G. Steffan, and J. Rose, "Application-specific customization of soft processor microarchitecture," in Proc. Int. Symp. FPGA, 2006, pp. 201-210.
    • (2006) Proc. Int. Symp. FPGA , pp. 201-210
    • Yiannacouras, P.1    Steffan, J.G.2    Rose, J.3
  • 8
    • 33749549867 scopus 로고    scopus 로고
    • S5: The architecture and development flow of a software configurable processor
    • Dec
    • J. M. Arnold, "S5: The architecture and development flow of a software configurable processor," in Proc. Int. Conf. FPL, Dec. 2005, pp. 121-128.
    • (2005) Proc. Int. Conf. FPL , pp. 121-128
    • Arnold, J.M.1
  • 9
    • 0031360911 scopus 로고    scopus 로고
    • Garp: A MIPS processor with a reconfigurable coprocessor
    • K. L. Pocek and J. Arnold, Eds, Online, Available
    • J. R. Hauser and J. Wawrzynek, "Garp: A MIPS processor with a reconfigurable coprocessor," in Proc. IEEE Symp. FPGAs Custom Comput. Mach., K. L. Pocek and J. Arnold, Eds., 1997, pp. 12-21. [Online]. Available: http://www.citeseer.ist.psu.edu/hauser97garp.html
    • (1997) Proc. IEEE Symp. FPGAs Custom Comput. Mach , pp. 12-21
    • Hauser, J.R.1    Wawrzynek, J.2
  • 11
    • 24944503384 scopus 로고    scopus 로고
    • A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning
    • R. Lysecky and F. Vahid, "A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning," in Proc. DATE, 2005, pp. 18-23.
    • (2005) Proc. DATE , pp. 18-23
    • Lysecky, R.1    Vahid, F.2
  • 12
    • 33646393297 scopus 로고    scopus 로고
    • CUSTARD - A customisable threaded FPGA soft processor and tools
    • Aug
    • R. Dimond, O. Mencer, and W. Luk, "CUSTARD - A customisable threaded FPGA soft processor and tools," in Proc. Int. Conf. FPL, Aug. 2005, pp. 1-6.
    • (2005) Proc. Int. Conf. FPL , pp. 1-6
    • Dimond, R.1    Mencer, O.2    Luk, W.3
  • 14
    • 2342501770 scopus 로고    scopus 로고
    • Synthesis-driven exploration of pipelined embedded processors
    • P. Mishra, A. Kejariwal, and N. Dutt, "Synthesis-driven exploration of pipelined embedded processors," in Proc. VLSI Des., 2004, pp. 921-926.
    • (2004) Proc. VLSI Des , pp. 921-926
    • Mishra, P.1    Kejariwal, A.2    Dutt, N.3
  • 17
    • 33846596515 scopus 로고    scopus 로고
    • G. Gibeling, A. Schultz, and K. Asanovic, RAMP architecture description language, in Proc. Workshop Architecture Res. Using FPGA Platforms, 2006, pp. 4-8. Proc. 12th Int. Symp. on High-Performance Computer Architecture.
    • G. Gibeling, A. Schultz, and K. Asanovic, "RAMP architecture description language," in Proc. Workshop Architecture Res. Using FPGA Platforms, 2006, pp. 4-8. Proc. 12th Int. Symp. on High-Performance Computer Architecture.
  • 19
    • 33846563322 scopus 로고    scopus 로고
    • P. Yiannacouras, The microarchitecture of FPGA-based soft processors, M.S. thesis, Univ. Toronto, Toronto, ON, 2005. [Online]. Available: http://www.eecg.toronto.edu/~jayar/pubs/theses/Yiannacouras/ PeterYiannacouras.pdf
    • P. Yiannacouras, "The microarchitecture of FPGA-based soft processors," M.S. thesis, Univ. Toronto, Toronto, ON, 2005. [Online]. Available: http://www.eecg.toronto.edu/~jayar/pubs/theses/Yiannacouras/ PeterYiannacouras.pdf
  • 20
    • 33846638584 scopus 로고    scopus 로고
    • Online, Available
    • _, SPREE. [Online], Available: http://www.eecg.utoronto.ca/ ~yiannac/SPREE/
    • SPREE
    • Gray, J.1
  • 21
    • 33846625483 scopus 로고    scopus 로고
    • MINT Simulation Software. (1996, Jan. 13). Univ. Rochester, Rochester, NY. [Online] Available: http://www.cs.rochester.edu/u/veenstra/
    • MINT Simulation Software. (1996, Jan. 13). Univ. Rochester, Rochester, NY. [Online] Available: http://www.cs.rochester.edu/u/veenstra/
  • 23
    • 33846615348 scopus 로고    scopus 로고
    • Altera Corporation, Private Communication
    • R. Cliff, Altera Corporation, Private Communication, 2005.
    • (2005)
    • Cliff, R.1
  • 24
    • 84962779213 scopus 로고    scopus 로고
    • MiBench: A free, commercially representative embedded benchmark suite
    • Dec
    • M. Guthaus et al., "MiBench: A free, commercially representative embedded benchmark suite," in Proc. IEEE 4th Annu. Workshop Workload Characterisation, Dec. 2001, pp. 3-14.
    • (2001) Proc. IEEE 4th Annu. Workshop Workload Characterisation , pp. 3-14
    • Guthaus, M.1
  • 25
  • 26
    • 33846592175 scopus 로고
    • May 25, Freescale, Online, Available
    • Dhrystone 2.1. (1988, May 25). Freescale. [Online], Available: http://www.freescale.com
    • (1988) Dhrystone 2.1
  • 27
    • 33846599632 scopus 로고    scopus 로고
    • Mar. 27, Univ. Toronto Toronto, ON, Canada, Online, Available
    • RATES - A Reconfigurable Architecture TEsting Suite. (2003, Mar. 27). Univ. Toronto Toronto, ON, Canada. [Online], Available: http://www. eecg.utoronto.ca/~lesley/benchmarks/rates/
    • (2003) RATES - A Reconfigurable Architecture TEsting Suite
  • 28
    • 33846641532 scopus 로고    scopus 로고
    • Jul, Altera, San Jose, CA, Online, Available
    • Stratix Device Handbook. (2005, Jul.). Altera, San Jose, CA. [Online]. Available: http://www.altera.com/literature/lit-stx.jsp
    • (2005) Stratix Device Handbook
  • 29
    • 21244499783 scopus 로고    scopus 로고
    • Optimizing a high-performance 32-bit processor for programmable logic
    • P. Metzgen, "Optimizing a high-performance 32-bit processor for programmable logic," in Proc. Int. Symp. Syst.-on-Chip, 2004, p. 13.
    • (2004) Proc. Int. Symp. Syst.-on-Chip , pp. 13
    • Metzgen, P.1
  • 30
    • 47349130731 scopus 로고    scopus 로고
    • Internet nuggets
    • Sep
    • J. Mashey, "Internet nuggets," Comput. Archit. News, vol. 32, no. 4, pp. 1-14, Sep. 2004.
    • (2004) Comput. Archit. News , vol.32 , Issue.4 , pp. 1-14
    • Mashey, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.