Embedded floating-point units in FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2006, Pages 12-20

  Beauchamp, Michael J ^a   Hauck, Scott ^a   Underwood, Keith D ^b   Hemmert, K Scott ^b  

^a UNIVERSITY OF WASHINGTON   (United States)

^b SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

Floating Point; FPGA; FPGA Architecture; FPU

Indexed keywords

COMPUTATIONAL GEOMETRY; COMPUTER AIDED ANALYSIS; DIGITAL ARITHMETIC; EMBEDDED SYSTEMS;

COMPUTATIONAL RESOURCES; FLOATING-POINTS; FPGA ARCHITECTURE; FPU;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33745868036     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1117201.1117204     Document Type: Conference Paper

References (19)

1. K. D. Underwood and K. S. Hemmert. Closing the gap: CPU and FPGA Trends in sustainable floating-point BLAS performance. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, 2004.
2. K. S. Hemmert and K. D. Underwood. An Analysis of the Double-Precision Floating-Point FFT on FPGAs. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA 2005.
3. M. de Lorimier and A. DeHon. Floating point sparse matrix-vector multiply for FPGAs. In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2005.
4. th Reconfigurable Architectures Workshop (RAW), Santa Fe, NM, April 2004.
5. th International Parallel and Distributed Processing Symposium (IPDPS'04), Santa Fe, NM, April 2004.
6. L. Zhuo and V. K. Prasanna. Sparse matrix-vector multiplication on FPGAs. In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2005.
7. K. D. Underwood. FPGAs vs. CPUs: Trends in Peak Floating-Point Performance. In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2004.
8. IEEE Standards Board. IEEE standard for binary floating-point arithmetic. Technical Report ANSI/IEEE Std. 754-1985, The Institute of Electrical and Electronic Engineers, New York, 1985.
9. nd Edition, A.K. Peters, Ltd. Natick, MA 2002.
10. Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet. June 2005 (Rev 4.3), [cited Aug 2005], http://direct.xilinx.com/bvdocs/publications/ds083.pdf.
11. Virtex-4 Family Overview. June 2005 (Rev 1.4), [cited Sept 2005], http://direct.xilinx.com/bvdocs/publications/ds112.pdf.
12. th International Workshop on Field-Programmable Logic and Applications, pp 213-222, 1997.
13. V. Betz and J. Rose. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Boston, MA 1999.
14. Xilinx: ASMBL Architecture. 2005 [cited Sept 2005], http://www.xilinx.com/products/silicon_solutions/rbgas/virtex/virtex4/overview/
15. Virtex-4 Data Sheet: DC and Switching Characteristics. Aug 2005 (Rev 1.9), [cited Sept 2005], http://direct.xilinx.com/bvdocs/publications/ds302.pdf
16. Virtex-II Platform FPGAs: Complete Data Sheet. Mar 2005 (Rev 3.4), [cited Aug 2005], http://direct.xilinx.com/bvdocs/publications/ds031.pdf
17. MIPS Technologies, Inc. 64-Bit Cores, MIPS64 Family Features. 2005, [cited Jan 2005], http://www.mips.com/content/Products/Cores/64-BitCores.
18. rd workshop on Memory performance issues, Munich, Germany, 2004.
19. B. Hutchings, P. Bellows, J. Hawkins, K. S. Hemmert, B. Nelson, and M. Rytting. A CAD Suite for High-Performance FPGA Design. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, April 1999.