An energy and power consumption analysis of FPGA routing architectures

Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Volumn , Issue , 2009, Pages 324-327

  Jamieson, Peter ^a   Luk, Wayne ^b   Wilton, Steve J E ^c   Constantinides, George A ^b  

^a MIAMI UNIVERSITY   (United States)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

^c UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BI-DIRECTIONAL; CLOCK FREQUENCY; CRITICAL PATH DELAYS; ENERGY CONSUMPTION; ENERGY EFFICIENT; FPGA ARCHITECTURES; FPGA VENDORS; MOBILE DOMAINS; POWER CONSUMPTION; POWER CONSUMPTION ANALYSIS; POWER ESTIMATIONS; ROUTING ARCHITECTURE; ROUTING BUFFERS;

MOBILE TELECOMMUNICATION SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77949379091     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2009.5377675     Document Type: Conference Paper

References (16)

1. Actel. Igloo Handbook, Jan 2008.
2. Altera. Stratix III Device Handbook, 2006.
3. J. Anderson and F. Najm. Power estimation techniques for FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(10):1015-1027, October 2004.
4. M. Atia, J. Bowles, D. W. Clarke, M. P. Henry, I. Page, J. Randall, and J. Yang. A self-validating temperature sensor implemented in fpgas. In FPL, pages 321-330, 1995.
5. D. Lewis et. al. The Stratix II Logic and Routing Architecture. In ACM/SIGDA International Symposium on FPGAs, pages 14-20, Feb 2005.
6. P. Jamieson, T. Becker, W. Luk, P. Cheung, and T. Rissa. Benchmarking Reconfigurable Architectures in the Mobile Domain. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2009.
7. I. Kuon and J. Rose. Automated transistor sizing for FPGA architecture exploration. In DAC '08, pages 792-795, 2008.
8. G. Lemieux and D. Lewis. Using Sparse Crossbars within LUT clusters. In ACM/SIGDA International Symposium on FPGAs, pages 59-68, Feb 2001.
9. G. Lemieux and D. Lewis. Directional and Single-Driver Wires in FPGA Interconnect. In IEEE International Conference on Field-Programmable Technology, pages 41-48, Dec 2004.
10. J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. M. Fang, and J. Rose. VPR 5.0: FPGA CAD and Architecture xploration Tools with Single-Driver Routing, Heterogeneity and Process Scaling. In ACM/SIGDA International Symposium on FPGAs, Feb 2009.
11. K. K. W. Poon, S. J. E. Wilton, and A. Yan. A detailed power model for field-programmable gate arrays. ACM Trans. Des. Autom. Electron. Syst., 10(2):279-302, 2005.
12. L. Shang, A. S. Kaviani, and K. Bathala. Dynamic power consumption in Virtex-II FPGA family. In FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, pages 157-164, 2002.
13. SiliconBlue. iCE DiCE: iCE65L04 Ultra Low-Power FPGA Known Good Die, Sep 2008.
14. T. Todman, G. Constantinides, S. Wilton, O. Mencer, W. Luk, and P. Cheung. Reconfigurable computing: architectures and design methods. IEE Proceedings - Computers and Digital Techniques, 152(2):193-207, 2005.
15. Xilinx. Virtex-5 Family Overview, June 2006.
16. S. Yang. Logic Synthesis and Optimization Benchmarks, Version 3.0. Tech. Report. Microelectronics Centre of North Carolina. P.O. Box 12889, Research Triangle Park, NC 27709 USA, 1991.