Timing-driven placement for hierarchical programmable logic devices

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2001, Pages 3-11

  Hutton, M ^a   Adibsamii, K ^a   Leaver, A ^a  

^a ALTERA CORPORATION   (United States)

Author keywords

Algorithm; CPLD; FPGA; Heuristic algorithm; Partitioning; Placement; Programmable logic; Timing driven placement

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; HEURISTIC METHODS; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; TIME MEASUREMENT;

TIMING-DRIVEN PLACEMENT;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 0035022183     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/360276.360286     Document Type: Conference Paper

References (17)