Design considerations for regular fabrics

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2004, Pages 97-102

  Sherlekar, Deepak D ^a  

^a Virage Logic   (United States)

Author keywords

Regular fabric; Structured ASIC

Indexed keywords

ALGORITHMS; AUTOMATION; ELECTRIC POWER DISTRIBUTION; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; INTERFACES (MATERIALS); MICROPROCESSOR CHIPS; NAND CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; SEMICONDUCTOR DEVICES;

POWER CONSUMPTION; REGULAR FABRIC; STRUCTURED ASIC; SYSTEM ON CHIPS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 2942659249     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/981066.981087     Document Type: Conference Paper

References (6)

1. Gheewala, Tushar R. Gate Array Cell Architecture and Routing Scheme. U.S. Patent 5923059, July1999.
2. Gheewala, Tushar R. Integrated Circuit Cell Architecture and Routing Scheme. U.S. Patent 5898194, April1999.
3. Gheewala, Tushar R. Integrated Circuit Cell Architecture and Routing Scheme. U.S. Patent 5923059, July1999.
4. Gheewala, Tushar R. Reduced Area Gate Array Cell Design Based on Shifted Placement of alternate Rows of Cells. U.S. Patent 5923060, July 1999.
5. Gheewala, Tushar R. Power and Signal Routing Technique for Gate Array Design. U.S. Patent 6091090, July2000.
6. Patel, Chetan, et al. An Architectural Exploration of Via Patterned Gate Arrays. ISPD Proceedings, April 2003.