An FPGA-based VLIW processor with custom hardware execution

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2005, Pages 107-117

  Jones, Alex K ^a   Fazekas, Joshua ^a   Hoare, Raymond ^a   Kusic, Dara ^a   Foster, John ^a  

^a PA 15260   (United States)

Author keywords

Algorithms; Design; Performance

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; DATA REDUCTION; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC PROGRAMMING; PROGRAM PROCESSORS; SHIFT REGISTERS;

COMPUTATIONAL KERNELS; CUSTOM HARDWARE EXECUTION; SEQUENTIAL PROCESSORS; SINGLE DATA STREAM ARCHITECTURE;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 20344380201     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1046192.1046207     Document Type: Conference Paper

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