Design of an NoC interface macrocell with hardware support of advanced networking functionalities

IEEE Transactions on Computers

Volumn 63, Issue 3, 2014, Pages 609-621

  Saponara, Sergio ^a   Bacchillone, Tony ^a   Petri, Esa ^b   Fanucci, Luca ^a   Locatelli, Riccardo ^c   Coppola, Marcello ^c  

^a UNIVERSITY OF PISA   (Italy)

^b Consorzio Pisa Ricerche ^*  (Italy)

^c STMICROELECTRONICS   (France)

Author keywords

Intellectual Property (IP); Multi Processor System on Chip (MPSoC); Network Interface (NI); Network on Chip (NoC); VLSI architectures

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPLEX NETWORKS; HARDWARE; INTELLECTUAL PROPERTY; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; NETWORK PROTOCOLS; QUALITY OF SERVICE; VLSI CIRCUITS;

END-TO-END PROTOCOL; INTELLECTUAL PROPERTY CORES; MULTI PROCESSOR SYSTEM ON CHIPS; NETWORK ON CHIP; NETWORK-INTERFACE (NI); ON CHIP COMMUNICATION; SCALABLE ARCHITECTURES; VLSI ARCHITECTURES;

DESIGN;

EID: 84897475340     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.70     Document Type: Article

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