A high-performance network interface architecture for NoCs using reorder buffer sharing

Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2010

Volumn , Issue , 2010, Pages 546-550

  Ebrahimi, Masoumeh ^a   Daneshtalab, Masoud ^a   Liljeberg, Pasi ^a   Plosila, Juha ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH PERFORMANCE NETWORKS; HYBRID NETWORK; IP CORE; M-TECHNOLOGIES; MEMORY ACCESS; MEMORY BANDWIDTHS; NETWORK INTERFACE ARCHITECTURE; ON-CHIP NETWORKS; PROPOSED ARCHITECTURES; RE-ORDER BUFFERS; RESOURCE UTILIZATIONS; SYNTHETIC TESTS;

COMPUTER ARCHITECTURE; INTERNET PROTOCOLS;

NETWORK ARCHITECTURE;

EID: 77952643051     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2010.77     Document Type: Conference Paper

References (12)

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