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Volumn , Issue , 2010, Pages 31-36

Network interface to synchronize multiple packets on NoC-based Systems-on-Chip

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH VARIATION; CMOS TECHNOLOGY; DATA DEPENDENCIES; DATA SYNCHRONIZATION; H.264 VIDEO DECODER; HETEROGENEOUS CORES; NETWORK INTERFACE; NETWORKS ON CHIPS; SYNCHRONIZATION MECHANISMS; SYNCHRONIZATION PROBLEM; SYSTEM-ON-CHIP; SYSTEMS ON CHIPS; TRAFFIC BEHAVIOR;

EID: 78650938227     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642627     Document Type: Conference Paper
Times cited : (9)

References (18)
  • 3
    • 33749613794 scopus 로고    scopus 로고
    • Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
    • E. Beigne and P. Vi vet, "Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture", ASYNC, pp. 172-183, 2006.
    • (2006) ASYNC , pp. 172-183
    • Beigne, E.1    Vi Vet, P.2
  • 4
    • 70349292542 scopus 로고    scopus 로고
    • Design and Implementation of a GALS Adapter for ANoC Based Architectures
    • Y. Thonnart et al., "Design and Implementation of a GALS Adapter for ANoC Based Architectures", ASYNC, pp. 13-22,2009.
    • (2009) ASYNC , pp. 13-22
    • Thonnart, Y.1
  • 5
    • 51549105542 scopus 로고    scopus 로고
    • Interfacing Cores and Routers in Network-on-Chip Using GALS
    • S. Kundu and S. Chattopadhyay, "Interfacing Cores and Routers in Network-on-Chip Using GALS", ISIC, pp. 154-157,2007.
    • (2007) ISIC , pp. 154-157
    • Kundu, S.1    Chattopadhyay, S.2
  • 7
    • 70449134695 scopus 로고    scopus 로고
    • NIUGAP: Low Latency Network Interface Architecture with Gray Code for Networks-on-Chip
    • D. Kim et aI., "NIUGAP: Low Latency Network Interface Architecture with Gray Code for Networks-on-Chip", ISCAS, pp. 3901-3905,2006.
    • (2006) ISCAS , pp. 3901-3905
    • Kim, D.1
  • 10
    • 36349024692 scopus 로고    scopus 로고
    • Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures
    • I. Panades and A. Greiner, "Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures" - NOCS, pp. 83-94, 2007.
    • (2007) NOCS , pp. 83-94
    • Panades, I.1    Greiner, A.2
  • 13
    • 85015586212 scopus 로고    scopus 로고
    • A Design Methodology for Application-Specific Networkson-Chip
    • J. Xu et al., "A Design Methodology for Application-Specific Networkson-Chip", TECS, pp. 263-280, 2006.
    • (2006) TECS , pp. 263-280
    • Xu, J.1
  • 14
    • 77955997714 scopus 로고    scopus 로고
    • System-Level Modeling of a Noc-Based H.264 Decoder
    • A. Agarwal et al., "System-Level Modeling of a Noc-Based H.264 Decoder", Annual IEEE Systems Conference, pp. 1-7,2008.
    • (2008) Annual IEEE Systems Conference , pp. 1-7
    • Agarwal, A.1
  • 15
    • 67650673064 scopus 로고    scopus 로고
    • Star-Mesh NoC Based Multi-Channel H.264 Decoder Design
    • J. Chang et al., "Star-Mesh NoC Based Multi-Channel H.264 Decoder Design", International SoC Design Conference, pp. 170-173,2008 .
    • (2008) International SoC Design Conference , pp. 170-173
    • Chang, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.