Secure memory accesses on networks-on-chip

IEEE Transactions on Computers

Volumn 57, Issue 9, 2008, Pages 1216-1229

  Fiorin, Leandro ^a   Palermo, Gianluca ^b   Lukovic, Slobodan ^a   Catalano, Valerio ^c   Silvano, Cristina ^b  

^a UNIVERSITY OF LUGANO   (Switzerland)

^b POLITECNICO DI MILANO   (Italy)

^c STMICROELECTRONICS   (France)

Author keywords

Data protection; Embedded systems; Multiprocessor System on Chip (MPSoC); Networks on Chip (NoCs); Security

Indexed keywords

DATA PROCESSING; ELECTRIC BREAKDOWN; ELECTRIC NETWORK TOPOLOGY; INTERNET;

ACCESS RIGHTS; ACCESSING DATA; AUTHENTICATION TECHNIQUES; COMMUNICATION INFRASTRUCTURES; DATA PROTECTION; DYNAMIC ENVIRONMENTS; DYNAMIC UPDATING; EMBEDDED DEVICES; EMBEDDED SYSTEMS; MEMORY ACCESSES; MULTI-PROCESSOR SYSTEMS; MULTIPROCESSOR SYSTEM-ON-CHIP (MPSOC); NETWORK INTERFACES; NETWORK LATENCIES; NETWORK-ON-CHIP; NETWORKS ON CHIPS; NETWORKS-ON-CHIP (NOCS); NOC ARCHITECTURES; PAPER ADDRESSES; PROCESSING ELEMENTS; RUN-TIME CONFIGURATION; SECURITY; SECURITY MANAGER; SHARED MEMORIES;

DATA STORAGE EQUIPMENT;

EID: 49149125905     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.69     Document Type: Article

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